Superconducting Single Flux Quantum (SFQ) logic with switching delay of 1ps and switching energy of 10 −19 J is a potential emerging candidate for replacing Complementary Metal Oxide Semiconductor (CMOS) to achieve very high speed and ultra energy efficiency. Conventional SFQ circuits need Full Path Balancing (FPB), which tends to require insertion of many path balancing buffers (D-Flip-Flops). FPB method increases total power consumption as well as total area of the chip. This article presents a novel scheme for realization of superconducting SFQ circuits by introducing a new depth-bounded graph partitioning algorithm in combination with a dual clocking method (slow and fast clock pulses) that minimizes the aforesaid path balancing overheads. Experimental results show that the proposed solution reduces total number of path balancing buffers and total static power consumption by an average of 2.68× and 60%, respectively, when compared to the best of other methods for realizing SFQ circuits. However, our scheme degrades the peak throughput; therefore, it is especially valuable when the actual throughput of the SFQ circuit is much lower than the peak theoretical throughput. This is typically the case due to high-level data dependencies of the application that feeds data into an SFQ circuit.

中文翻译：

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实现超导SFQ电路的深度有界图划分算法和双时钟方法

具有开关延迟的超导单通量量子 (SFQ) 逻辑1ps和 10 的开关能量-19 Ĵ是替代互补金属氧化物半导体 (CMOS) 以实现非常高的速度和超高能效的潜在新兴候选者。传统的 SFQ 电路需要全路径平衡 (FPB)，这往往需要插入许多路径平衡缓冲器 (D-Flip-Flops)。FPB 方法增加了总功耗以及芯片的总面积。本文提出了一种实现超导 SFQ 电路的新方案，它引入了一种新的深度有界图分割算法，并结合了双时钟方法（慢速和快速时钟脉冲），最大限度地减少了上述路径平衡开销。实验结果表明，所提出的解决方案将路径平衡缓冲区的总数和总静态功耗分别平均降低了 2.68 倍和 60%，与实现 SFQ 电路的其他最佳方法相比。然而，我们的方案降低了峰值吞吐量；因此，当 SFQ 电路的实际吞吐量远低于峰值理论吞吐量时，它尤其有价值。这通常是由于将数据馈送到 SFQ 电路的应用程序的高级数据依赖性所致。