Detection of level shifts in a noisy signal, or trend break detection, is a problem that appears in several research fields, from biophysics to optics and economics. Although many algorithms have been developed to deal with such a problem, accurate and low-complexity trend break detection is still an active topic of research. The Linearized Bregman Iterations have been recently presented as a low-complexity and computationally efficient algorithm to tackle this problem, with a formidable structure that could benefit immensely from hardware implementation. In this work, a hardware architecture of the Linearized Bregman Iteration algorithm is presented and tested on a Field Programmable Gate Array (FPGA). The hardware is synthesized in different-sized FPGAs, and the percentage of used hardware, as well as the maximum frequency enabled by the design, indicate that an approximately 100 gain factor in processing time, concerning the software implementation, can be achieved. This represents a tremendous advantage in using a dedicated unit for trend break detection applications. The proposed architecture is compared with a state-of-the-art hardware structure for sparse estimation, and the results indicate that its performance concerning trend break detection is much more pronounced while, at the same time, being the indicated solution for long datasets.

从生物物理学到光学和经济学，检测噪声信号中的电平变化或趋势中断检测是在多个研究领域中出现的问题。尽管已经开发了许多算法来处理这种问题，但是准确和低复杂度的趋势中断检测仍然是研究的活跃主题。线性化的Bregman迭代最近已被提出来解决此问题，它是一种低复杂度且计算效率高的算法，其强大的结构可以极大地受益于硬件实现。在这项工作中，提出了线性化Bregman迭代算法的硬件架构，并在现场可编程门阵列（FPGA）上对其进行了测试。硬件是在不同大小的FPGA中合成的，所用硬件的百分比以及设计支持的最大频率，表示在软件实现方面，可以在处理时间上获得大约100的增益因子。在将专用单元用于趋势中断检测应用程序中，这代表了巨大的优势。将所提出的体系结构与最新的硬件结构进行稀疏估计进行了比较，结果表明，其与趋势断裂检测有关的性能更为显着，同时也是长数据集的理想解决方案。