Abstract The thickness increase of gallium nitride (GaN) cap layer from 2 nm to 35 nm to achieve an enhancement mode GaN MIS-HEMT (Metal-Insulator-Semiconductor High-Electron-Mobility Transistor) with a threshold voltage (Vth) of +0.5 V is studied using TCAD simulations. The simulations are calibrated to measured I-V characteristics of the 1 μm gate length GaN MIS-HEMT with the 2 nm thick GaN cap. A good agreement at low and high drain voltages (VDS=1 V and 5 V) between simulations and measurements is achieved by using a quantum-corrected drift-diffusion transport model. The enhancement mode GaN MIS-HEMT with a GaN cap thickness of 35 nm achieves Vth = + 0.5 V thanks to positive interface traps occurring between the SiN passivation layer and the GaN cap as reported experimentally. The simulations indicate that a parasitic channel is created at the interface between the SiN layer and the 35 nm GaN cap. Our study also shows an increase in the breakdown voltage from 100 V to 870 V when a thickness of the GaN cap layer increases from 15 nm to 35 nm.

中文翻译：

---

SiN/GaN帽界面电荷和GaN帽层的作用实现增强型GaN MIS-HEMT操作

摘要 氮化镓 (GaN) 盖层的厚度从 2 nm 增加到 35 nm，以实现阈值电压 (Vth) 为 +0.5 的增强型 GaN MIS-HEMT（金属-绝缘体-半导体高电子迁移率晶体管） V 使用 TCAD 模拟进行研究。模拟被校准为具有 2 nm 厚 GaN 帽的 1 μm 栅极长度 GaN MIS-HEMT 的测量 IV 特性。通过使用量子校正漂移扩散传输模型，模拟和测量之间在低和高漏极电压（VDS = 1 V 和 5 V）下实现了良好的一致性。具有 35 nm GaN 帽盖厚度的增强型 GaN MIS-HEMT 实现了 Vth = + 0.5 V，这要归功于实验报道的 SiN 钝化层和 GaN 帽盖之间发生的正界面陷阱。模拟表明在 SiN 层和 35 nm GaN 帽之间的界面处产生了一个寄生通道。我们的研究还表明，当 GaN 盖层的厚度从 15 nm 增加到 35 nm 时，击穿电压从 100 V 增加到 870 V。