We investigate the reliability of state-of-the-art SiGe heterojunction bipolar transistors (HBTs) in 55-nm technology under mixed-mode stress. We perform electrical characterization and implement a TCAD model calibrated on the measurement data to describe the increased base current degradation at different collector-base voltages. We introduce a simple and self-consistent simulation methodology that links the observed degradation trend to interface traps generation at the emitter/base spacer oxide ascribed to hot holes generated by impact ionization (II) in the collector/base depletion region. This effectively circumvents the limitations of commercial TCAD tools that do not allow II to be the driving force of the degradation. The approach accounts for self-heating and electric fields distribution allowing to reproduce measurement data including the deviation from the power-law behavior.

中文翻译：

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规模化 SiGe HBT 中碰撞电离引起的混合模式应力的表征和 TCAD 建模


我们研究了采用 55 nm 技术的最先进的 SiGe 异质结双极晶体管 (HBT) 在混合模式应力下的可靠性。我们执行电气特性分析并实施根据测量数据校准的 TCAD 模型，以描述不同集电极-基极电压下增加的基极电流衰减。我们引入了一种简单且自洽的模拟方法，该方法将观察到的退化趋势与发射极/基极隔离氧化物处的界面陷阱生成联系起来，该陷阱归因于集电极/基极耗尽区中碰撞电离（II）产生的热空穴。这有效地规避了商业 TCAD 工具的局限性，即不允许 II 成为退化的驱动力。该方法考虑了自热和电场分布，允许重现测量数据，包括幂律行为的偏差。