Logic-in-memory (LiM) circuits based on resistive random access memory (RRAM) devices and the material implication logic are promising candidates for the development of low-power computing devices that could fulfill the growing demand of distributed computing systems. However, these circuits are affected by many reliability challenges that arise from device nonidealities (e.g., variability) and the characteristics of the employed circuit architecture. Thus, an accurate investigation of the variability at the array level is needed to evaluate the reliability and performance of such circuit architectures. In this work, we explore the reliability and performance of smart IMPLY (SIMPLY) (i.e., a recently proposed LiM architecture with improved reliability and performance) on two 4-kb RRAM arrays based on different resistive switching oxides integrated in the back end of line (BEOL) of the 0.25- $\mu \text{m}$ BiCMOS process. We analyze the tradeoff between reliability and energy consumption of SIMPLY architecture by exploiting the results of an extensive array-level variability characterization of the two technologies. Finally, we study the worst case performance of a full adder implemented with the SIMPLY architecture and benchmark it on the analogous CMOS implementation.

中文翻译：

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电阻式存储器阵列中存储器中逻辑电路的可靠性

基于电阻式随机存取存储器 (RRAM) 器件和材料蕴涵逻辑的存储器中逻辑 (LiM) 电路是开发低功耗计算设备的有希望的候选者，可以满足分布式计算系统不断增长的需求。然而，这些电路受到许多可靠性挑战的影响，这些挑战源于器件的非理想性（例如可变性）和所采用的电路架构的特性。因此，需要对阵列级别的可变性进行准确调查，以评估此类电路架构的可靠性和性能。在这项工作中，我们探索了智能 IMPLY (SIMPLY)（即，最近提出的具有更高可靠性和性能的 LiM 架构），基于集成在 0.25-$\mu\text{m}$ BiCMOS 工艺的后端（BEOL）中的不同电阻开关氧化物的两个 4-kb RRAM 阵列。我们通过利用两种技术的广泛阵列级可变性表征的结果来分析 SIMPLY 架构的可靠性和能耗之间的权衡。最后，我们研究了用 SIMPLY 架构实现的全加器的最坏情况性能，并在类似的 CMOS 实现上对其进行了基准测试。我们通过利用两种技术的广泛阵列级可变性表征的结果来分析 SIMPLY 架构的可靠性和能耗之间的权衡。最后，我们研究了用 SIMPLY 架构实现的全加器的最坏情况性能，并在类似的 CMOS 实现上对其进行了基准测试。我们通过利用两种技术的广泛阵列级可变性表征的结果来分析 SIMPLY 架构的可靠性和能耗之间的权衡。最后，我们研究了用 SIMPLY 架构实现的全加器的最坏情况性能，并在类似的 CMOS 实现上对其进行了基准测试。