The requirement of multilevel cell (MLC) resistive random access memory (RRAM) for computing is different than that for MLC storage. It generally requires a linearly spaced conductance median and an ultratight conductance distribution, as the column current are summed up for analog computation. In this article, 3-bit per cell RRAM that is suitable for accurate inference of a deep neural network (DNN) is demonstrated, with ultratight conductance distribution (<1.5% sigma). First, a two-loop write–verify protocol is proposed. Then, statistical experiments are conducted on RRAM array fabricated in Winbond’s 90-nm process. By incorporating the measured conductance distribution into DNN simulation considering the real weight mapping, inference accuracy with only 0.5% degradation over software baseline is achieved for CIFAR-10 data set even when 128 rows are read-out in parallel. By enabling parallel read-out, the system-level energy efficiency and throughput could be improved by $5.3 \times $ and $4.4 \times $ , respectively, compared to the 3-bit per cell RRAM used as MLC storage.

中文翻译：

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每单元 3 位电阻式存储器的阵列级编程及其在深度神经网络推理中的应用

多级单元 (MLC) 电阻式随机存取存储器 (RRAM) 的计算要求与 MLC 存储的要求不同。它通常需要线性间隔的电导中值和超紧密电导分布，因为列电流是为模拟计算求和的。在本文中，展示了适用于深度神经网络 (DNN) 精确推理的每单元 3 位 RRAM，具有超紧密电导分布 (<1.5% sigma)。首先，提出了一个双循环写验证协议。然后，对华邦 90 纳米工艺制造的 RRAM 阵列进行了统计实验。通过将测量的电导分布纳入考虑真实权重映射的 DNN 模拟，推理精度仅为 0。即使并行读出 128 行，CIFAR-10 数据集的性能也比软件基线降低了 5%。通过启用并行读出，可以通过以下方式提高系统级能效和吞吐量 $5.3 \times $ 和 $4.4 \times $ 分别与用作 MLC 存储的每单元 3 位 RRAM 相比。