Substrate-bias-affected unique electrical characteristics of junctionless transistors (JLTs) were investigated in detail. Bulk channel thickness of JLTs ( ${t}_{\mathrm {si\_{}eff}}$ ) was effectively modulated by back-gate bias ( ${V}_{\text {gb}}$ ). The variation in threshold voltage ( ${V}_{\text {th}}$ ) $\vphantom {^{\int }}$ and mobility degradation were observed in the reduced ${t}_{\mathrm {si\_{}eff}}$ , due to the negative ${V}_{\text {gb}}$ -induced depletion of free electrons. The ${V}_{\text {gb}}$ effect was also influenced significantly by the doping concentration in JLTs. In addition, numerical simulations verified those results and analytical equations explained well the experimental results.

中文翻译：

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通过衬底偏置控制无结晶体管的有效沟道厚度

详细研究了受基板偏置影响的无结晶体管 (JLT) 的独特电气特性。JLT 的大通道厚度 ( ${t}_{\mathrm {si\_{}eff}}$ ) 被背栅偏置有效调制 ( ${V}_{\text {gb}}$ ）。阈值电压的变化（ ${V}_{\text {th}}$ ) $\vphantom {^{\int }}$ 和迁移率下降观察到减少 ${t}_{\mathrm {si\_{}eff}}$ ，由于负 ${V}_{\text {gb}}$ - 引起自由电子耗尽。这 ${V}_{\text {gb}}$ JLTs 中的掺杂浓度也显着影响了效果。此外，数值模拟验证了这些结果，解析方程很好地解释了实验结果。