We present the results of low-noise silicon junction field-effect transistors (JFET) with a split-channel concept. The device can be manufactured as a module in a standard CMOS process. The channel is split under the top gate of the JFET into a source-side main channel and a drain-side-extended drain channel. Devices with design gate length between 1.0 and 3.0 $\mu \text{m}$ and effective channel length between 0.1 and 2.2 $\mu \text{m}$ were fabricated. It is shown that transconductance and channel resistance are dominated by the overlap between the main channel and the top gate. Output resistance can be enhanced by increasing the overlap of the extended drain channel with the top gate. A cutoff frequency of up to 2.5 GHz, 60-mS/mm maximum transconductance, and an intrinsic gain of 2200 were achieved. For the main channel length below ${1}~\mu \text{m}$ , a strong roll-off behavior of the threshold voltage is observed. The flicker-corner frequency for 1/f noise is 500 Hz. Above 1 kHz, a value of 2.5-nV/ ${\sqrt {\text {Hz}}}$ input-referred voltage noise density at 0.3-pF input capacitance was achieved. Also, a brief comparison to devices from other publications is presented.

中文翻译：

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分离通道概念增强的低噪声 Si-JFET

我们展示了具有分离通道概念的低噪声硅结场效应晶体管 (JFET) 的结果。该器件可以在标准 CMOS 工艺中制造为模块。沟道在 JFET 的顶栅下方分成源极侧主沟道和漏极侧扩展漏极沟道。设计栅极长度介于 1.0 和 3.0 之间的器件 $\mu \text{m}$ 有效通道长度介于 0.1 和 2.2 之间 $\mu \text{m}$ 被捏造。结果表明，跨导和沟道电阻由主沟道和顶栅之间的重叠决定。可以通过增加扩展漏极沟道与顶栅的重叠来提高输出电阻。实现了高达 2.5 GHz 的截止频率、60-mS/mm 的最大跨导和 2200 的固有增益。对于以下主通道长度 ${1}~\mu \text{m}$ ，观察到阈值电压的强烈滚降行为。1/f 噪声的闪烁角频率为 500 Hz。高于 1 kHz，值为 2.5-nV/ ${\sqrt {\text {Hz}}}$ 在 0.3pF 输入电容下实现了输入参考电压噪声密度。此外，还介绍了与其他出版物中的设备的简要比较。