This article describes a wideband low-noise frequency synthesizer implemented in 0.13- $\mu \text{m}$ SiGe BiCMOS process for 5G millimeter-wave applications. To extend the frequency range while reducing the phase noise, a fundamental voltage-controlled oscillator (VCO) array including four Colpitts VCO cores with switchable bias circuits is adopted in the proposed frequency synthesizer. A ring-oscillator-based injection locked frequency divider is utilized as the wideband divide-by-2 prescaler, and its bandwidth is optimized based on a new injection-locked behavior model. This fabricated frequency synthesizer can be locked in a range from 23 to 36.8 GHz (46.2%) by a 100-MHz step. It achieves a phase noise of −94.7 dBc/Hz at the 1-MHz offset and an output power of −3.5 dBm measured at 36.8 GHz. The chip consumes 360.6 mW from 3.3 and 1.8 V supplies and has an area of $2.7\times3.1$ mm².

中文翻译：

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具有基本 Colpitts VCO 阵列的 23-36.8-GHz 低噪声频率合成器，采用 SiGe BiCMOS，用于 5G 应用

本文描述了一个在 0.13- 中实现的宽带低噪声频率合成器 $\mu \text{m}$ 用于 5G 毫米波应用的 SiGe BiCMOS 工艺。为了在降低相位噪声的同时扩展频率范围，在所提出的频率合成器中采用了包括四个 Colpitts VCO 内核和可切换偏置电路的基本压控振荡器 (VCO) 阵列。将基于环形振荡器的注入锁定分频器用作宽带 2 分频预分频器，其带宽基于新的注入锁定行为模型进行优化。这种制造的频率合成器可以以 100 MHz 的步长锁定在 23 至 36.8 GHz (46.2%) 的范围内。它在 1 MHz 偏移处实现了 −94.7 dBc/Hz 的相位噪声，在 36.8 GHz 下测量的输出功率为 −3.5 dBm。该芯片从 3.3 和 1.8 V 电源消耗 360.6 mW，面积为 $2.7\times3.1$ 毫米²。