This article presents the theoretical analyses and experimental results about jitter tolerance for delay-locked loop (DLL)-based clock and data recovery (CDR), which is generally used in an embedded clock serial link. From the proposed S-domain model, we prove that DLL-based CDR has superior low-frequency jitter tolerance than PLL-based CDR, whereas, assuming the ideal case, high-frequency jitter tolerance of DLL-based CDR is only a half of that of PLL-based CDR. In addition, the jitter tolerance characteristics of both PLL- and DLL-based CDRs are analyzed in a practical environment. Finally, the consistency of analysis is verified from measurement results using 2.7-Gb/s enhanced reduced-voltage differential signaling (eRVDS) receiver.

中文翻译：

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基于 DLL 的时钟和数据恢复电路的分析抖动容限模型

本文介绍了基于延迟锁定环 (DLL) 的时钟和数据恢复 (CDR) 的抖动容限的理论分析和实验结果，该系统通常用于嵌入式时钟串行链路。从提出的 S 域模型中，我们证明基于 DLL 的 CDR 比基于 PLL 的 CDR 具有更好的低频抖动容限，而在理想情况下，基于 DLL 的 CDR 的高频抖动容限仅为其一半基于 PLL 的 CDR。此外，在实际环境中分析了基于 PLL 和 DLL 的 CDR 的抖动容限特性。最后，使用 2.7 Gb/s 增强型降压差分信号 (eRVDS) 接收器的测量结果验证了分析的一致性。