Recently, extensive research attention has been drawn to the program executing security of embedded processor since increasing code tamper attacks, as well as transient faults severely affect the safety of embedded systems. The security monitoring and fault recovery technique is one of the effective methods to ensure the security and performance of embedded devices. In this article, an architecture for the security monitoring and fault recovery is proposed for run-time program execution, which builds a Monitoring Cache (M-Cache) and then checks the integrity based on reference data. Especially, the proposed architecture will build the checkpoint once the M-Cache is missed and also take the rollback operation after the unsuccessful of integrity check. In addition, three tampered positions (e.g., instruction register within the pipeline, instruction within the cache, and code within memory) have been elaborately focused on to guarantee the normal running of the embedded system. Eventually, by adopting the open RISC processor for algorithm implementation and verification, the proposal has been proven to be promising for the detection of a fault or tampered program, as well as the fast recovery of running environment and code.

中文翻译：

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一种基于M-Cache的嵌入式处理器安全监控和故障恢复架构

近年来，随着代码篡改攻击的增多以及瞬态故障严重影响嵌入式系统的安全，嵌入式处理器的程序执行安全性引起了广泛的研究关注。安全监控和故障恢复技术是保证嵌入式设备安全和性能的有效方法之一。在本文中，提出了一种用于运行时程序执行的安全监控和故障恢复架构，该架构构建了一个监控缓存（M-Cache），然后根据参考数据检查完整性。特别是，所提出的架构将在 M-Cache 丢失时建立检查点，并在完整性检查不成功后进行回滚操作。此外，三个被篡改的位置（例如，流水线中的指令寄存器、缓存中的指令和内存中的代码）精心设计，以保证嵌入式系统的正常运行。最终，通过采用开放的RISC处理器进行算法实现和验证，该方案被证明在检测故障或篡改程序以及快速恢复运行环境和代码方面具有良好的前景。