当前位置: X-MOL 学术IEEE Trans. Very Larg. Scale Integr. Syst. › 论文详情
Our official English website, www.x-mol.net, welcomes your feedback! (Note: you will need to create a separate account there.)
Design Methodology for Distributed Large-Scale ERSFQ Bias Networks
IEEE Transactions on Very Large Scale Integration (VLSI) Systems ( IF 2.8 ) Pub Date : 2020-11-01 , DOI: 10.1109/tvlsi.2020.3023054
Gleb Krylov , Eby G. Friedman

Rapid single-flux quantum (RSFQ) circuits have recently attracted considerable attention as a promising cryogenic beyond CMOS technology for exascale computing. Energy-efficient RSFQ (ERSFQ) is an energy-efficient, inductive bias scheme for RSFQ circuits, where the power dissipation is drastically lowered by eliminating the bias resistors, while the cell library remains unchanged. An ERSFQ bias scheme requires the introduction of multiple circuit elements—current limiting Josephson junctions, bias inductors, and feeding Josephson transmission lines (FJTLs). In this article, parameter guidelines and design techniques for ERSFQ circuits are presented. The proposed guidelines enable more robust circuits resistant to severe variations in supplied bias currents. Trends are considered, and advantageous tradeoffs are discussed for the different components within a bias network. The guidelines provide a means to decrease the size of an FJTL and, thereby, reduce the physical area, power dissipation, and overall bias currents, supporting further increases in circuit complexity. A distributed approach to ERSFQ FJTL is also presented to simplify placement and minimize the effects of the parasitic inductance of the bias lines. This methodology and related circuit techniques are applicable to automating the synthesis of bias networks to enable large-scale ERSFQ circuits.

中文翻译:

分布式大规模 ERSFQ 偏置网络的设计方法

快速单通量量子 (RSFQ) 电路作为一种用于百亿亿次计算的超越 CMOS 技术的有前途的低温技术,最近引起了相当大的关注。高能效 RSFQ (ERSFQ) 是一种用于 RSFQ 电路的高能效电感偏置方案,其中通过消除偏置电阻大大降低了功耗,而单元库保持不变。ERSFQ 偏置方案需要引入多个电路元件——限流约瑟夫森结、偏置电感器和馈电约瑟夫森传输线 (FJTL)。在本文中,介绍了 ERSFQ 电路的参数指南和设计技术。所提议的指导方针能够使电路更加稳健,能够抵抗所提供偏置电流的严重变化。考虑趋势,并针对偏置网络中的不同组件讨论了有利的权衡。该指南提供了一种减小 FJTL 尺寸的方法,从而减少物理面积、功耗和整体偏置电流,支持进一步增加电路复杂性。还介绍了 ERSFQ FJTL 的分布式方法,以简化放置并最大限度地减少偏置线寄生电感的影响。这种方法和相关电路技术适用于偏置网络的自动化合成,以实现大规模 ERSFQ 电路。还介绍了 ERSFQ FJTL 的分布式方法,以简化放置并最大限度地减少偏置线寄生电感的影响。这种方法和相关电路技术适用于偏置网络的自动化合成,以实现大规模 ERSFQ 电路。还介绍了 ERSFQ FJTL 的分布式方法,以简化放置并最大限度地减少偏置线寄生电感的影响。这种方法和相关电路技术适用于偏置网络的自动化合成,以实现大规模 ERSFQ 电路。
更新日期:2020-11-01
down
wechat
bug