Machine learning applications, especially deep neural networks (DNNs) have seen ubiquitous use in computer vision, speech recognition, and robotics. However, the growing complexity of DNN models have necessitated efficient hardware implementations. The key compute primitives of DNNs are matrix vector multiplications, which lead to significant data movement between memory and processing units in today's von Neumann systems. A promising alternative would be colocating memory and processing elements, which can be further extended to performing computations inside the memory itself. We believe in-memory computing is a propitious candidate for future DNN accelerators, since it mitigates the memory wall bottleneck. In this article, we discuss various in-memory computing primitives in both CMOS and emerging nonvolatile memory (NVM) technologies. Subsequently, we describe how such primitives can be incorporated in standalone machine learning accelerator architectures. Finally, we analyze the challenges associated with designing such in-memory computing accelerators and explore future opportunities.

中文翻译：

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基于内存计算的机器学习加速器的电路和架构

机器学习应用程序，尤其是深度神经网络 (DNN)，在计算机视觉、语音识别和机器人技术中无处不在。然而，DNN 模型日益复杂，需要高效的硬件实现。DNN 的关键计算原语是矩阵向量乘法，这会导致当今冯诺依曼系统中内存和处理单元之间的大量数据移动。一个有希望的替代方案是将内存和处理元素并置，这可以进一步扩展到在内存本身内部执行计算。我们相信内存计算是未来 DNN 加速器的有利候选者，因为它可以缓解内存墙瓶颈。在本文中，我们将讨论 CMOS 和新兴的非易失性存储器 (NVM) 技术中的各种内存计算原语。随后，我们描述了如何将这些原语合并到独立的机器学习加速器架构中。最后，我们分析了与设计此类内存计算加速器相关的挑战并探索未来的机会。