The rapid evolution of field-programmable gate array (FPGA) devices has strongly influenced both the design methodology and development tools. This article describes an original implementation based on a hardware structure used for static and dynamic task scheduling. The proposed custom processor has hardware-implemented RTOS (HW-RTOS) features and is verified using an FPGA circuit. The solution replaces the classical stack save concept with a resource remapping mechanism that enables a new task to be executed starting with the next processor cycle. The proposed hardware scheduler enables unified management of events and interrupts, by implementing a method of attaching interrupts to tasks while ensuring the requirements of real-time systems. The robustness and performance of the proposed platform are guaranteed by the context switch operations, presence of the intertask synchronization and communication mechanisms, and by the efficient use of the multiplexed resources. Instead of saving and restoring general-purpose registers into the memory, the latency is removed by directly commuting the datapath task resources.

中文翻译：

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自定义 CPU 实现上的实时事件处理和抢占式硬件 RTOS 调度

现场可编程门阵列 (FPGA) 设备的快速发展极大地影响了设计方法和开发工具。本文描述了基于用于静态和动态任务调度的硬件结构的原始实现。建议的定制处理器具有硬件实现的 RTOS (HW-RTOS) 功能，并使用 FPGA 电路进行验证。该解决方案用资源重新映射机制取代了经典的堆栈保存概念，该机制使新任务能够从下一个处理器周期开始执行。所提出的硬件调度程序通过实现一种将中断附加到任务的方法，同时确保实时系统的要求，从而能够统一管理事件和中断。所提出平台的鲁棒性和性能由上下文切换操作保证，任务间同步和通信机制的存在，以及多路复用资源的有效利用。不是将通用寄存器保存和恢复到内存中，而是通过直接交换数据路径任务资源来消除延迟。