This paper presents a 4-bit 36 GS/s analog-to-digital converter (ADC) employing eight time-interleaved (TI) flash sub-ADCs in 40 nm complementary metal-oxide-semiconductor (CMOS) process. A wideband front-end matching circuit based on a peaking inductor is designed to increase the analog input bandwidth to 18 GHz. A novel offset calibration that can achieve quick detection and accurate correction without affecting the speed of the comparator is proposed, guaranteeing the high-speed operation of the ADC. A clock distribution circuit based on CMOS and current mode logic (CML) is implemented in the proposed ADC, which not only maintains the speed and quality of the high-speed clock, but also reduces the overall power consumption. A timing mismatch calibration is integrated into the chip to achieve fast timing mismatch detection of the input signal which is bandlimited to the Nyquist frequency for the complete ADC system. The experimental results show that the differential nonlinearity (DNL) and integral nonlinearity (INL) are −0.28/+0.22 least significant bit (LSB) and −0.19/+0.16 LSB, respectively. The signal-to-noise-and-distortion ratio (SNDR) is above 22.5 dB and the spurious free dynamic range (SFDR) is better than 35 dB at 1.2 GHz. An SFDR above 24.5 dB and an SNDR above 18.6 dB across the entire Nyquist frequency can be achieved. With a die size of 2.96 mm * 1.8 mm, the ADC consumes 780 mW from the 0.9/1.2/1.8 V power supply.

中文翻译：

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在40 nm CMOS工艺中具有18 GHz模拟带宽的4位36 GS / s ADC

本文提出了一种采用40 nm互补金属氧化物半导体（CMOS）工艺的，采用八个时间交错（TI）闪存子ADC的4位36 GS / s模数转换器（ADC）。设计了基于峰值电感器的宽带前端匹配电路，以将模拟输入带宽增加到18 GHz。提出了一种新颖的失调校准，可以在不影响比较器速度的情况下实现快速检测和准确校正，从而保证了ADC的高速运行。所提出的ADC中实现了一种基于CMOS和电流模式逻辑（CML）的时钟分配电路，不仅保持了高速时钟的速度和质量，而且降低了总功耗。时序失配校准集成到芯片中，以实现对输入信号的快速时序失配检测，该信号的带宽限制为整个ADC系统的奈奎斯特频率。实验结果表明，微分非线性（DNL）和积分非线性（INL）分别为-0.28 / + 0.22最低有效位（LSB）和-0.19 / + 0.16 LSB。在1.2 GHz时，信噪比（SNDR）高于22.5 dB，无杂散动态范围（SFDR）优于35 dB。整个奈奎斯特频率上的SFDR高于24.5 dB，SNDR高于18.6 dB。裸片尺寸为2.96 mm * 1.8 mm，ADC从0.9 / 1.2 / 1.8 V电源消耗的功率为780 mW。实验结果表明，微分非线性（DNL）和积分非线性（INL）分别为-0.28 / + 0.22最低有效位（LSB）和-0.19 / + 0.16 LSB。在1.2 GHz时，信噪比（SNDR）高于22.5 dB，无杂散动态范围（SFDR）优于35 dB。整个奈奎斯特频率上的SFDR高于24.5 dB，SNDR高于18.6 dB。裸片尺寸为2.96 mm * 1.8 mm，ADC从0.9 / 1.2 / 1.8 V电源消耗的功率为780 mW。实验结果表明，微分非线性（DNL）和积分非线性（INL）分别为-0.28 / + 0.22最低有效位（LSB）和-0.19 / + 0.16 LSB。在1.2 GHz时，信噪比（SNDR）高于22.5 dB，无杂散动态范围（SFDR）优于35 dB。整个奈奎斯特频率上的SFDR高于24.5 dB，SNDR高于18.6 dB。裸片尺寸为2.96 mm * 1.8 mm，ADC从0.9 / 1.2 / 1.8 V电源消耗的功率为780 mW。在整个奈奎斯特频率上可达到6 dB。裸片尺寸为2.96 mm * 1.8 mm，ADC从0.9 / 1.2 / 1.8 V电源消耗的功率为780 mW。在整个奈奎斯特频率上可达到6 dB。裸片尺寸为2.96 mm * 1.8 mm，ADC从0.9 / 1.2 / 1.8 V电源消耗的功率为780 mW。