In this paper, we propose a novel fault tolerant methodology for digital pipelined data-paths called Control Feedback Loop Error Decimation (CFLED), that reduces the error magnitude at the outputs. The data-path is regarded from a control perspective as a process affected by perturbations or faults. Based on the corresponding dynamic model, we design feedback control loops with the goal of attenuating the effect of the faults on the output. The correction loops apply correction factors to selected data-path registers from blocks that have their execution rewinded. We apply the proposed methodology on the data-path of a controller designed for a 2-degree of freedom robot arm, and compare the cost and reliability to the generic triple modular redundancy. For Field Programmable Gate Array (FPGA) technology, the solution we propose uses 30% less slices with respect to Triple Modular Redundancy (TMR), while having a third less digital signal processing blocks. Simulation results show that our approach improves the reliability and error detection.

中文翻译：

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通过控制反馈回路的容错数字数据路径设计

在本文中，我们为数字流水线数据路径提出了一种新颖的容错方法，称为控制反馈环路误差抽取（CFLED），它可以减小输出的误差幅度。从控制角度看，数据路径是受干扰或故障影响的过程。基于相应的动态模型，我们设计了反馈控制回路，其目的是减轻故障对输出的影响。校正循环将校正因子应用于从执行后退的块中选择的数据路径寄存器。我们将拟议的方法应用于为2自由度机械臂设计的控制器的数据路径，并将成本和可靠性与通用三重模块冗余进行比较。对于现场可编程门阵列（FPGA）技术，我们提出的解决方案相对于三重模块冗余（TMR）使用的切片减少了30％，而数字信号处理模块减少了三分之一。仿真结果表明，我们的方法提高了可靠性和错误检测率。