The utilization of usual supply voltage and clock for repetitive state transistors in digital circuits is a fundamental driver for high power utilization. Most significant bit states of the counter stay longer than the least significant bit states and it has some repetitive states. To limit the supply voltage and stop the clock for MSB Flip Flop (FF) transistor, our method uses Control Combinational Logic, Voltage selector and Modified Integrated Clock Gating blocks. The LSB transistor always have a supply voltage of 1.2V and succession of the clock, while MSB transistor gets just 480mV and the clock will be stopped by the this technique. Bring down the supply voltage and quit the clock for redundant states either 0 or 1 in MSB. Meantime supply 1.2V and clock for state changes over from one state to next state. The experimental simulation was done in 45nm CMOS technology using Cadence virtuoso indicates that this asynchronous counter achieves a power savings of 23.57% and the same modified technique when applied to the counters with transmission-gate FF, hybrid-latch FF and sense amplifier FF will have more than 40% power savings and the technique applied in some benchmark circuits will have more than 22% power savings than existing techniques.

中文翻译：

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通过提供双电源和修改的时钟门控来适应计数器冗余位，以支持VLSI中的低功耗

数字电路中重复状态晶体管的通常电源电压和时钟的利用是高功率利用的基本驱动器。计数器的最高有效位状态比最低有效位状态停留的时间更长，并且具有一些重复状态。为了限制电源电压并停止MSB触发器（FF）晶体管的时钟，我们的方法使用了控制组合逻辑，电压选择器和改进的集成时钟门控模块。LSB晶体管始终具有1.2V的电源电压并具有时钟连续性，而MSB晶体管仅具有480mV的电压，并且该技术将停止时钟。降低电源电压并退出时钟，以获得MSB中0或1的冗余状态。同时电源1.2V和状态时钟从一个状态转换到下一个状态。