In this article, we focus on developing predictive upset models to characterize the nonpersistent effects of large-signal gate-side injection on n-type and p-type metal-oxide semiconductor field-effect transistors (mosfets). By “nonpersistent,” we refer to a set of conditions that do not affect the physical characteristics of the device or exhibit any memory effects, i.e., the device will operate normally once the injected large signal stimulus is removed. We present predictive models that determine the maximum limits for large-signal gate-side injection in terms of the device's ION/IOFF ratio prior to degradation or damage to the device. A function based on the mosfet technology device parameters, such as its threshold voltage and its power supply rating, is developed and presented. We then validate our predictive models against experimentally measured data for complementary metal-oxide-semiconductor (CMOS) mosfet devices fabricated using 350, 180, 130, and 65 nm standard Taiwan Semiconductor Manufacturing Company (TSMC) CMOS processes. Based on our validated predictive models, we show how the maximum limits for large-signal gate-side injection at 10-MHz change with technology scaling, from ~9.7 dBm for 350 nm to ~-1.7 dBm for 65-nm technology nodes for n-type mosfets; and, from ~11.0 dBm for 350 nm down to ~1.2 dBm for 65-nm technology nodes for p-type mosfets. We anticipate that our predictive models can be leveraged by CMOS circuit designers and electromagnetic interference/compatibility (EMI/EMC) engineers as quick “rule of thumb” guidelines to estimate device and circuit level susceptibility for the injected large signals.

中文翻译：

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用于估计大信号栅极注入下 MOSFET 响应非持续效应极限的预测模型


在本文中，我们重点开发预测翻转模型，以表征大信号栅极侧注入对 n 型和 p 型金属氧化物半导体场效应晶体管 (MOSFET) 的非持续效应。我们所说的“非持久”是指一组不影响器件物理特性或表现出任何记忆效应的条件，即一旦注入的大信号刺激被移除，器件将正常运行。我们提出的预测模型可以在器件退化或损坏之前根据器件的 ION/IOFF 比来确定大信号栅极侧注入的最大限制。开发并提出了基于 MOSFET 技术器件参数（例如阈值电压和电源额定值）的函数。然后，我们根据使用 350、180、130 和 65 nm 标准台积电 (TSMC) CMOS 工艺制造的互补金属氧化物半导体 (CMOS) MOSFET 器件的实验测量数据来验证我们的预测模型。基于我们经过验证的预测模型，我们展示了 10 MHz 下大信号栅极侧注入的最大限制如何随技术扩展而变化，从 350 nm 的 ~9.7 dBm 到 65 nm 技术节点的 ~-1.7 dBm -型MOSFET；对于 p 型 MOSFET，从 350 nm 的约 11.0 dBm 降至 65 nm 技术节点的约 1.2 dBm。我们预计 CMOS 电路设计人员和电磁干扰/兼容性 (EMI/EMC) 工程师可以利用我们的预测模型作为快速“经验法则”指南来估计器件和电路级对注入大信号的敏感性。