A single event transient (SET) filtering technique for the Xilinx Artix-7 Field Programmable Gate Array (FPGA) is investigated experimentally. The technique combines AND – OR gate circuits to provide a single circuit that can dissipate SETs irrespective of whether the input state is high or low. It uses fewer resources than the widely used Triple Modular Redundancy (TMR) and significantly reduces event upsets in a FPGA.

This paper presents the results of the experimental investigation, with the SET filter applied to various sequential circuit configurations, by proton beam irradiation. Their implementation and evaluation in-beam show their efficiency in eliminating SETs and single event upsets (SEU) compared to unmitigated designs.

实验研究了Xilinx Artix-7现场可编程门阵列（FPGA）的单事件瞬态（SET）过滤技术。该技术结合了“与”或“或”门电路，以提供一个可以消除SET的电路，而与输入状态为高还是低无关。与广泛使用的三重模块冗余（TMR）相比，它使用的资源更少，并显着减少了FPGA中的事件中断。

本文介绍了通过质子束辐照将SET滤波器应用于各种顺序电路配置的实验研究结果。与未缓解的设计相比，它们在光束中的实施和评估显示出它们在消除SET和单事件翻转（SEU）方面的效率。