Decimal multiplication is one of the complex operations in the applications that still radix-10 representations are preferred. To improve the performance, Ahmed et al. proposed some fast and area efficient binary-to-decimal converters to be used for both partial product generation and partial product reduction stages of digit-by-digit decimal multiplication. These converters that transform each binary result to binary coded decimal (BCD) representation utilize two new types of binary-to-decimal converter cells in a cascading structure. These cells are called fast binary-to-decimal (FBD) and low-area binary-to-decimal (LABD) converters. In this paper, we show that despite the fact that their architectural framework for digit-by-digit decimal multiplication and the proposed hybrid multi-operand binary-to-decimal converter are correct, some logical equations presented for FBD converter cell are incorrect. Moreover, there exist ambiguities in presenting the logical equations of both FBD and LABD converter cells. Thus, we represent the correct and optimized equations for FBD and LABD converter cells using truth tables.

十进制乘法是应用程序中的复杂操作之一，仍然首选基数10表示。为了提高性能，Ahmed等人。提出了一些快速且面积有效的二进制到十进制转换器，用于数位十进制乘法的部分乘积生成和部分乘积缩减阶段。这些将每个二进制结果转换为二进制编码的十进制（BCD）表示形式的转换器在级联结构中利用了两种新型的二进制到十进制转换器单元。这些单元称为快速二进制到十进制（FBD）和低面积二进制到十进制（LABD）转换器。在本文中，我们表明，尽管它们的逐位十进制乘法的体系结构框架和所提出的混合多操作数二进制至十进制转换器是正确的，为FBD转换器单元提供的一些逻辑方程式不正确。此外，在呈现FBD和LABD转换器单元的逻辑方程式方面存在歧义。因此，我们使用真值表来表示FBD和LABD转换器单元的正确和优化方程。