Die-stacked DRAM has emerged as an effective approach to address the memory bandwidth wall as it offers much higher bandwidth than off-chip DRAM. It is typically used along with much larger off-chip DRAM to form a hybrid memory system with sufficient capacity and abundant bandwidth. Lots of research activities have been drawn to exploit the potentials of such memory systems. One of the approaches is to use Die-stacked DRAM as a cache of off-chip DRAM. Judicious mechanisms have been proposed to manage these on-chip DRAM caches with tailored line sizes, fetch sizes, replacement policies, and allocation mechanisms. One such example is Footprint Cache [16] which uses 2KB lines but populates each line with only referenced 64B blocks to avoid transferring dead blocks. Doing so significantly reduces the traffic between on-chip DRAM and off-chip DRAM.

In this paper, we propose to extend the idea of Decoupled Sector Cache [32] to the DRAM Cache by allowing multiple sparsely populated lines to be coalesced and stored in one DRAM Cache line (we call it Line-Coalescing DRAM Cache (LCDC)). Our experimental results show that LCDC can effectively increase the utilization of on-chip DRAM and provide 16.7% performance boost over prior designs. In addition, it is orthogonal with many existing DRAM Cache techniques and can work with them to increase the performance improvement to 27.5% and achieve 89.1% of the performance of an ideal DRAM Cache design.

模堆叠DRAM已经成为解决内存带宽壁垒的有效方法，因为它提供的带宽比片外DRAM高得多。它通常与更大的片外DRAM一起使用，以形成具有足够容量和充足带宽的混合存储系统。为了利用这种存储系统的潜力，进行了许多研究活动。其中一种方法是使用管芯堆叠DRAM作为片外DRAM的缓存。已经提出了明智的机制来使用定制的行大小，访存大小，替换策略和分配机制来管理这些片上DRAM缓存。这样的例子就是足迹缓存[16]使用2KB的行，但每行仅填充了引用的64B块，以避免传输死块。这样做显着减少了片上DRAM和片外DRAM之间的流量。

在本文中，我们建议通过允许将多个稀疏填充的行合并并存储在一个DRAM缓存行中来将去耦扇区缓存[32]的概念扩展到DRAM缓存（我们称其为行合并DRAM缓存（LCDC））。 。我们的实验结果表明，LCDC可以有效提高片上DRAM的利用率，并比以前的设计提供16.7％的性能提升。此外，它与许多现有的DRAM缓存技术正交，可以与它们一起使用，以将性能提升提高到27.5％，并达到理想DRAM缓存设计的89.1％的性能。