High performance system‐on‐chip (SoCs) designs have led to high‐density integrated circuits using field programmable gate arrays (FPGAs) for rapid prototyping and reconfigurable digital circuits. Using FPGA reconfigurability, it is possible to design a configurable network‐on‐chip (NoC) for different applications. NoC architectures provide efficient communication infrastructures for implementing very large SoCs. In this article, we propose HiFMP, a high‐performance FPGA‐based multicrossbar prioritized NoC router. The aim followed by the proposed router is designing a low‐power NoC router with high performance in terms of energy‐efficiency, network throughput, area, and latency for efficient FPGA realization. HiFMP is a parameterizable router, and is effectively used for an FPGA‐based NoC with mesh topology. Performance evaluations include network‐level analysis and hardware exploration; the results demonstrate the effectiveness and high performance of HiFMP in terms of latency, throughput, power consumption, and area, comparing with the existing related architectures.

中文翻译：

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高性能基于FPGA的多交叉开关优先级片上网络

高性能片上系统（SoC）设计导致了使用现场可编程门阵列（FPGA）进行快速原型设计和可重构数字电路的高密度集成电路。利用FPGA可重配置性，可以为不同的应用设计可配置的片上网络（NoC）。NoC架构提供了用于实现超大型SoC的高效​​通信基础架构。在本文中，我们提出了HiFMP，这是一种高性能的基于FPGA的多交叉优先级NoC路由器。拟议路由器的目标是设计一种低功耗NoC路由器，以提高其能效，网络吞吐量，面积和延迟，从而实现高效的FPGA。HiFMP是可参数化的路由器，可有效地用于具有网状拓扑的基于FPGA的NoC。性能评估包括网络级分析和硬件探索；结果表明，与现有的相关体系结构相比，HiFMP在延迟，吞吐量，功耗和面积方面均具有高效率和高性能。