The last two decades have seen a revolution in telecom technology with the evolution of three wireless mobile communication standards, namely, GPRS to 3G, 3G to 4G, and 4G to 5G. 5G offers faster download speeds and enables high connectivity between devices such as mobile phones, displays, smart homes, and smart cars because of its high reliability and high bandwidths (up to 10 Gbps). However, at the same time, data and personal information are also more susceptible to theft because of the high connectivity. Such threats can be addressed using electronic data encryption using the advanced encryption standard (AES). Because of their reconfigurable and parallel architectures, Field-Programmable Gate Arrays (FPGAs) are getting popular in VLSI design flows to enable the pre-silicon validation of designs faster data rates in real-time. FPGAs also serve as platforms for software development in the pre-silicon environment owing to their faster speeds. The design community is also heavily relying on High-Level Synthesis (HLS) tools in VLSI design flows. HLS platforms enable the new designs to improve the process with sustained authentication between two analytical selections from conventional functional specifications. We propose a high-throughput FPGA implementation based on high-level Synthesis for the AES algorithm. The implementation uses a 128-bit key and is highly suited for telecom applications such as 5G. Researchers have developed and tested the setup and then used the Vivado HLS tool to evaluate various HLS guidelines as per the implementation. The generated Verilog RTL was verified and implemented on Xilinx Kintex 7 and Virtex 6 FPGAs. Since using the same resources, we have seen significant results than existing methods achieved by individual investigators. We have also verified the design for functionality by checking the ciphertext output from our design against a reference design output for the same input plaintext.

在过去的二十年中，随着GPRS到3G，3G到4G和4G到5G三种无线移动通信标准的演进，电信技术发生了革命。5G具有更高的可靠性和高带宽（高达10 Gbps），可提供更快的下载速度并实现手机，显示器，智能家居和智能汽车等设备之间的高度连接。但是，与此同时，由于高度的连接性，数据和个人信息也更容易被盗。可以使用高级加密标准（AES）使用电子数据加密来解决此类威胁。由于它们具有可重新配置和并行的架构，因此现场可编程门阵列（FPGA）在VLSI设计流程中变得越来越流行，从而能够以更快的数据速率实时进行设计的硅前验证。由于FPGA的速度较快，因此它们也可作为前硅环境中软件开发的平台。设计社区在VLSI设计流程中也高度依赖高级综合（HLS）工具。HLS平台使新设计能够通过对来自常规功能规范的两个分析选择之间的持续验证来改善流程。我们针对AES算法提出了一种基于高级综合的高吞吐量FPGA实现。该实现使用128位密钥，非常适合5G等电信应用。研究人员已经开发并测试了该设置，然后使用Vivado HLS工具根据实现评估了各种HLS指南。验证生成的Verilog RTL，并在Xilinx Kintex 7和Virtex 6 FPGA上实现。由于使用相同的资源，我们已经看到了比个别研究者所获得的现有方法显着的成果。我们还通过对照相同输入明文的参考设计输出来检查设计中的密文输出，来验证设计的功能性。