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High‐reliability gate driver circuit to prevent ripple voltage
Journal of the Society for Information Display ( IF 1.7 ) Pub Date : 2020-10-08 , DOI: 10.1002/jsid.969 Jungwoo Lee 1 , Jongsu Oh 1 , Eun Kyo Jung 1 , KeeChan Park 2 , Jae‐Hong Jeon 3 , Soo‐Yeon Lee 4 , Yong‐Sang Kim 1
Journal of the Society for Information Display ( IF 1.7 ) Pub Date : 2020-10-08 , DOI: 10.1002/jsid.969 Jungwoo Lee 1 , Jongsu Oh 1 , Eun Kyo Jung 1 , KeeChan Park 2 , Jae‐Hong Jeon 3 , Soo‐Yeon Lee 4 , Yong‐Sang Kim 1
Affiliation
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In this paper, a high‐reliability gate driver circuit is proposed to prevent multiple outputs. The proposed circuit ensures reliability of the pull‐up thin‐film transistor (TFT) by periodically discharging the Q node voltage to the low‐level voltage (VGL) in the off stage. In addition, the output node is composed of two pull‐down TFTs that are driven alternately to ensure stability against bias stress. Thus, because the reliabilities of the pull‐up and pull‐down TFTs can be guaranteed simultaneously, the stability of the entire circuit is improved. Based on the simulation results, the rising and falling times of the output pulse are stable within 1.77 and 1.28 μs, respectively, even when the threshold voltage of the entire TFT is shifted by +10.0 V. In addition, the ripple voltage of the proposed circuit is almost eliminated and is within 0.79% of the total swing voltage. Moreover, through current is prevented in the proposed circuit because the turn‐on durations of the pull‐up and pull‐down units are completely nonoverlapping, which suggests that unnecessary power consumption can be eliminated. Therefore, based on 2,160 stages, the total power consumption of the proposed circuit is reduced by 34.7 mW from 276.3 to 241.6 mW.
中文翻译：
高可靠性栅极驱动器电路可防止纹波电压
本文提出了一种高可靠性的栅极驱动器电路，以防止出现多个输出。所提出的电路通过在截止阶段将Q节点电压定期放电到低电平电压（VGL），来确保上拉薄膜晶体管（TFT）的可靠性。此外，输出节点由两个下拉TFT组成，这些TFT交替驱动以确保抵抗偏压的稳定性。因此，由于可以同时保证上拉和下拉TFT的可靠性，因此可以改善整个电路的稳定性。根据仿真结果，即使整个TFT的阈值电压偏移+10.0 V，输出脉冲的上升和下降时间也分别稳定在1.77和1.28μs内。此外，所提出的纹波电压电路几乎被消除并且在0以内。总摆幅电压的79％。此外，由于上拉单元和下拉单元的导通时间完全不重叠，因此在拟议的电路中可防止直通电流，这表明可以消除不必要的功耗。因此，基于2160级，该电路的总功耗从276.3降低到241.6 mW，降低了34.7 mW。
更新日期：2020-10-08
中文翻译：
高可靠性栅极驱动器电路可防止纹波电压
本文提出了一种高可靠性的栅极驱动器电路，以防止出现多个输出。所提出的电路通过在截止阶段将Q节点电压定期放电到低电平电压（VGL），来确保上拉薄膜晶体管（TFT）的可靠性。此外，输出节点由两个下拉TFT组成，这些TFT交替驱动以确保抵抗偏压的稳定性。因此，由于可以同时保证上拉和下拉TFT的可靠性，因此可以改善整个电路的稳定性。根据仿真结果，即使整个TFT的阈值电压偏移+10.0 V，输出脉冲的上升和下降时间也分别稳定在1.77和1.28μs内。此外，所提出的纹波电压电路几乎被消除并且在0以内。总摆幅电压的79％。此外，由于上拉单元和下拉单元的导通时间完全不重叠，因此在拟议的电路中可防止直通电流，这表明可以消除不必要的功耗。因此，基于2160级，该电路的总功耗从276.3降低到241.6 mW，降低了34.7 mW。
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