A 40 nm complementary metal oxide semiconductor carrier‐aggregated drive amplifier with high linearity is presented for sub‐GHz Internet of Things applications. The proposed drive amplifier consists of two high linear amplifiers, which are composed of five differential cascode cells. Carrier aggregation can be achieved by switching on both the driver amplifiers simultaneously and combining the two independent signals in the current mode. The common gate bias of the cascode cells is selected to maximize the output 1 dB compression point (P1dB) to support high‐linear wideband applications, and is used for the local supply voltage of digital circuitry for gain control. The proposed circuit achieved an output P1dB of 10.7 dBm with over 22.8 dBm of output 3rd‐order intercept point up to 0.9 GHz and demonstrated a 55 dBc adjacent channel leakage ratio (ACLR) for the 802.11af with −5 dBm channel power. To the best of our knowledge, this is the first demonstration of the wideband carrier‐aggregated drive amplifier that achieves the highest ACLR performance.

中文翻译：

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用于载波聚合的双路径高线性放大器

针对sub-GHz的物联网应用，提出了一种具有高线性度的40 nm互补金属氧化物半导体载波聚合驱动放大器。建议的驱动放大器由两个高线性放大器组成，两个放大器由五个差分共源共栅单元组成。载波聚合可以通过同时打开两个驱动器放大器并在当前模式下组合两个独立信号来实现。选择共源共栅单元的公共栅极偏置以最大化输出1 dB压缩点（P1dB），以支持高线性宽带应用，并将其用于数字电路的本地电源电压以进行增益控制。拟议的电路实现了10.7 dBm的输出P1dB，超过22.8 dBm的输出三阶交调点最高为0。9 GHz，并展示了具有-5 dBm信道功率的802.11af的55 dBc相邻信道泄漏比（ACLR）。就我们所知，这是实现最高ACLR性能的宽带载波聚合驱动放大器的首次演示。