We have proposed a reconfigurable high speed and very economical Rapid Single Flux Quantum (RSFQ) superconducting logic design based on the Fast Fourier Transform (FFT) Processor. We have designed a 256 – point FFT processor with the help of a bit-slicing block sharing unit. RSFQ is one of the superconducting device logics comprises of Josephson Junction. The computation complexity of this superconducting FFT is less when the number of points increased. We have proposed three different designs depending on the split radix FFT, the bit-serial radix 2 FFT, and the mixed radix FFT algorithms. The proposed design will slice the 256 – point FFT into eight 32 – point FFT each and each 32 – point FFT is divided into eight 4 – point FFT each for the reduction in hardware cost. For complex multiplication, the computation complexity of our design will be less than N/2 Log₂ N for the radix 2 algorithm based on the Block share processing Unit (BSPU) and further, it is reduced for split radix & mixed radix algorithms based on BSPU based RSFQ logic. Due to this, the speed of the processor is improvised compared to general FFT algorithm based semiconductor technology. we have computed and calculated the latency at 10 GHz for our designs. The main aim of this proposed design is to reduce the complex computation time and better performance of the processor with less hardware cost. This proposed design can furthermore continue to several N² – point by using synchronous clock tree.

我们提出了一种基于快速傅立叶变换（FFT）处理器的可重构高速，非常经济的快速单通量量子（RSFQ）超导逻辑设计。我们借助位分块共享单元设计了一个256点FFT处理器。RSFQ是构成约瑟夫逊结的超导设备逻辑之一。当点数增加时，该超导FFT的计算复杂度降低。根据拆分基数FFT，位串行基数2 FFT和混合基数FFT算法，我们提出了三种不同的设计。拟议的设计将256点FFT分成8个32点FFT，每个32点FFT分为8个4点FFT，以降低硬件成本。对于复杂的乘法，₂ N用于基于块共享处理单元（BSPU）的基数2算法，此外，对于基于基于BSPU的RSFQ逻辑的拆分基数和混合基数算法，它减少了2N。因此，与基于常规FFT算法的半导体技术相比，处理器的速度有所提高。我们已经为我们的设计计算并计算了10 GHz的延迟。提出的设计的主要目的是减少复杂的计算时间并以更少的硬件成本获得更好的处理器性能。通过使用同步时钟树，该提议的设计还可以继续到几个N ² –点。