We propose a parasitic BJT-based zero capacitor random access memory (Z-RAM) cell suitable for stand-alone memory applications. In this Z-RAM cell, high-bandgap TiO\(_2\) is used as the source/drain material and silicon as the channel of an n-channel fully depleted silicon-on-insulator MOSFET. Using well-calibrated TCAD simulations, we demonstrate the programming of the proposed Z-RAM cell at low drain voltages, which is a major advantage from an application perspective. At low drain voltage, hole storage is initiated by band-to-band tunnelling, which is subsequently taken over by impact ionization. Large valence band offset between TiO\(_2\) and Si (\(\varDelta { E }_\mathrm{V }\approx\) 2 eV) is utilized for storing larger number of excess holes inside the body for a longer time. This leads to the improvement of both sense margin and retention time compared to an all-silicon Z-RAM cell. We predict a retention time of 2 s and 70 ms at \(T=300\) K and 358 K, respectively, for device gate length of 30 nm. We have optimized the device design to obtain a write ‘0’ time of 6 \(\upmu\)s. Multiple non-destructive reading operation for the proposed Z-RAM cell is also demonstrated.

我们提出一种适用于独立存储器应用的基于BJT的寄生零电容器随机存取存储器（Z-RAM）单元。在此Z-RAM单元中，高带隙TiO \（_ 2 \）被用作源极/漏极材料，硅被用作n沟道完全耗尽的绝缘体上硅MOSFET的沟道。使用经过良好校准的TCAD仿真，我们演示了在低漏极电压下对拟议Z-RAM单元进行编程的方法，从应用角度来看，这是一个主要优势。在低漏极电压下，空穴存储是通过带间隧穿开始的，随后通过碰撞电离来接管。TiO \（_ 2 \）与Si之间的价带偏移大（\（\ varDelta {E} _ \ mathrm {V} \ approx \）2 eV）用于在体内将大量多余的孔存储更长的时间。与全硅Z-RAM单元相比，这可改善感测裕度和保留时间。对于器件栅极长度为30 nm的情况，我们预计分别在\（T = 300 \） K和358 K下的保留时间为2 s和70 ms 。我们对器件设计进行了优化，以获得6 \（\ upmu \） s的写入“ 0”时间。还展示了针对所提出的Z-RAM单元的多个非破坏性读取操作。