Although we may be at the end of Moore's law, lowering chip power consumption is still the primary driving force for the designers. To enable low-power operation, we propose a resonant energy recovery static random access memory (SRAM). We propose the first series resonance scheme to reduce the dynamic power consumption of the SRAM operation. Besides, we identified the requirement of supply boosting of the write buffers for proper resonant operation. We evaluated the resonant 144KB SRAM cache through SPICE and test chip using a commercial 28nm CMOS technology. The experimental results show that the resonant SRAM can save up to 30% dynamic power at 1GHz operating frequency compared to the state-of-the-art design.

中文翻译：

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共振能量回收SRAM架构

尽管我们可能处于摩尔定律的尽头，但降低芯片功耗仍然是设计人员的主要驱动力。为了实现低功耗操作，我们提出了一种谐振能量恢复静态随机存取存储器 (SRAM)。我们提出了第一个串联谐振方案来降低 SRAM 操作的动态功耗。此外，我们确定了写入缓冲器的电源升压要求，以实现正确的谐振操作。我们通过 SPICE 和使用商用 28nm CMOS 技术的测试芯片评估了谐振 144KB SRAM 缓存。实验结果表明，与最先进的设计相比，谐振 SRAM 在 1GHz 工作频率下可以节省高达 30% 的动态功耗。