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Development of FPGA based phase alignment logic for the high speed protocol in HEP Experiments
Computer Physics Communications ( IF 7.2 ) Pub Date : 2021-02-01 , DOI: 10.1016/j.cpc.2020.107649
Shuaib Ahmad Khan , Jubin Mitra , Tapan K. Nayak

Abstract Experiments in high energy physics (HEP) operate at the forefront of detector technology, electronics, data acquisition (DAQ), data analysis, and computing. With the advent of high-energy accelerators running at large beam intensities, there is a great demand for radiation-hard high speed protocol for data transmission. Along with the detector data, communication signals like trigger, timing and control (TTC) information plays an important role. The TTC information needs to be transmitted over long distances using asynchronous communication links, which act as a bridge between the front-end radiation hard electronics and the DAQ. Maintaining the timing relationships and synchronization among payloads is an essential pre-requisite for the integrity of the acquired data. However, the phase relationship among the transmitted TTC signals gets disrupted due to the various sources of inter-signal interferences and channel link uncertainties. To address this challenge we have developed a phase alignment logic that can be applied over any asynchronous data-transmission protocol. We have implemented the proposed logic on the widely used radiation tolerant data-transmission protocol, called Gigabit Transceiver (GBT). The DAQ architecture needs to be resilient enough to avoid the loss of data or the errors in physics payload. The principal idea for implementation of the logic is to have an effective strategy to realign the synchronization without the need for power-on reset (PoR). The approach reduces the number of dead cycles that otherwise would have been utilized to minimize the timing errors. The chosen hardware for the experimental setup is 28 nm Stratix-V FPGA from Intel Inc. The benchmark of the system performance is illustrated in terms of the measurements of resource utilization, results of signal integrity, route delays, eye diagram and jitter analysis.

中文翻译:

为 HEP 实验中的高速协议开发基于 FPGA 的相位对齐逻辑

摘要 高能物理 (HEP) 实验处于检测器技术、电子学、数据采集 (DAQ)、数据分析和计算的最前沿。随着以大光束强度运行的高能加速器的出现,对用于数据传输的抗辐射高速协议有很大的需求。除了检测器数据外,触发、定时和控制 (TTC) 信息等通信信号也起着重要作用。TTC 信息需要使用异步通信链路进行长距离传输,作为前端抗辐射电子设备和 DAQ 之间的桥梁。保持有效载荷之间的时序关系和同步是获取数据完整性的必要先决条件。然而,由于信号间干扰和信道链路不确定性的各种来源,传输的 TTC 信号之间的相位关系被破坏。为了应对这一挑战,我们开发了一种相位对齐逻辑,可以应用于任何异步数据传输协议。我们已经在广泛使用的耐辐射数据传输协议(称为千兆位收发器 (GBT))上实现了所提议的逻辑。DAQ 架构需要具有足够的弹性,以避免数据丢失或物理负载中的错误。实现逻辑的主要思想是有一个有效的策略来重新调整同步,而无需上电复位 (PoR)。该方法减少了死循环的数量,否则会被用来最小化时序误差。
更新日期:2021-02-01
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