Polar codes are one of the most favorable capacity-achieving codes owing to their simple structures and low decoding complexity. Successive cancellation list (SCL) decoders with large list sizes achieve performances very close to those of maximum-likelihood (ML) decoders. However, hardware cost is a severe problem because an SCL decoder with list size L consists of L copies of a successive cancellation (SC) decoder. To address this issue, a stochastic SCL (SSCL) polar decoder is proposed. Although stochastic computing can achieve a good hardware reduction compared with the deterministic one, its straightforward application to an SCL decoder is not well-suited owing to the precision loss and severe latency. Therefore, a doubling probability approach and adaptive distributed sorting (DS) are introduced. A corresponding hardware architecture is also developed. Field programmable gate array (FPGA) results demonstrate that the proposed stochastic SCL polar decoder can achieve a good performance and complexity tradeoff.

极性码由于其简单的结构和较低的解码复杂性而成为最有利的容量实现代码之一。具有大列表大小的连续消除列表（SCL）解码器实现的性能非常接近最大似然（ML）解码器。然而，硬件成本是一个严重的问题，因为一个SCL解码器列表大小大号由大号连续消除（SC）解码器的副本。为了解决这个问题，提出了一种随机SCL（SSCL）极性解码器。尽管与确定性计算相比，随机计算可以实现良好的硬件缩减，但是由于精度损失和严重的延迟，其无法直接应用于SCL解码器。因此，引入了加倍概率方法和自适应分布式排序（DS）。还开发了相应的硬件体系结构。现场可编程门阵列（FPGA）的结果表明，所提出的随机SCL极性解码器可以实现良好的性能和复杂度的折衷。