This paper presents a single loop 3 ^rd order discrete-time Sigma–Delta Modulator ( ) using a single operational amplifier (Op-Amp). The proposed utilises delay-based discrete-time integrators and a single Op-Amp is used to implement all the integrators of the proposed design. The delay-based design helps in relaxing the settling time requirement of an integrator, also the error due to slewing in the output of the integrator is avoided. A switched capacitor Op-Amp based proposed design is simulated in standard 180~nm CMOS technology with a resolution of 10.75 bits. The proposed achieves a signal-to-noise-distortion ratio (SNDR) of 66.48 dB and dynamic range (DR) of 70 dB. An input signal of −4 dBFS magnitude at a frequency of 2.125 kHz is sampled with a sampling frequency of 1.024 MHz. The proposed circuit is designed for a bandwidth (BW) of 20 kHz with an over-sampling-ratio (OSR) of 25.6. The proposed modulator achieves a figure-of-merit (FOMS/FOMW) of 156.48 dB/0.290 (pJ/conversion-step) with the total power consumption of 20 µW at 1.8 V supply voltage (VDD). A Monte-Carlo simulation for the SNDR of the proposed design is done and the achieved mean and standard deviation (SD) is 66.09 dB and 1.025 respectively for 1000 samples.

中文翻译：

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67 dB SNDR 20 kHz BW SC三阶 $ \ Sigma \ Delta $ΣΔ 具有单个运算放大器和20 µW功耗的调制器，用于生物医学应用

本文提出了一种单回路3 ^次顺序离散时间Σ-Δ调制器（ ）使用单个运算放大器（Op-Amp）。建议利用基于延迟的离散时间积分器，并使用单个运算放大器来实现所提出设计的所有积分器。基于延迟的设计有助于减轻积分器的建立时间要求，还可以避免由于积分器输出的摆幅引起的误差。基于开关电容器Op-Amp的建议设计采用标准的180〜nm CMOS技术进行仿真，分辨率为10.75位。建议达到66.48 dB的信噪比（SNDR）和70 dB的动态范围（DR）。在1.025 MHz的采样频率下，以2.125 kHz的频率对−4 dBFS幅度的输入信号进行采样。提出的电路设计用于20 kHz的带宽（BW），过采样率（OSR）为25.6。所提出的调制器的品质因数（FOMS / FOMW）为156.48 dB / 0.290（pJ /转换步长），在1.8 V电源电压（VDD）下的总功耗为20 µW。对拟议设计的SNDR进行了蒙特卡洛仿真，对于1000个样本，获得的均值和标准差（SD）分别为66.09 dB和1.025。