Based on three groups of different offset voltages, a bandgap reference (BGR) and power-ON reset (POR) hybrid circuit is implemented in 65-nm CMOS. The BGR using amplifier offset voltage and current matching, and the POR using offset voltage comparison and loop settling feature, respectively, are proposed. This circuit, with low-quiescent current, not only generates a stable reference voltage independent of voltage and temperature variations, but also provides a high-robust supply-ramp-rate-tolerant power-ON/brown-out reset signal with a hysteretic window of 18–24 mV. Experimental results show that the circuit with line regulations (LNRs) of 2.63%–4.28%/V and temperature coefficients (TCs) of 22–32 ppm/°C across multiple chips has a power dissipation around $2.25~\mu \text{W}$ from a 1-V supply voltage. The circuit achieves a low noise density of 18.5 nV/ $\surd $ Hz at 100-Hz offset frequency and a good figure of merit (FoM) performance. With an active core area of 0.014 mm², the circuit has fixed reset trip voltages under the supply ramp time of 0.4–100 ms.

中文翻译：

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具有 2.25μA 电流耗散和低复杂性的低于 1V BGR 和 POR 混合电路

基于三组不同的偏移电压，在 65-nm CMOS 中实现了带隙基准 (BGR) 和上电复位 (POR) 混合电路。分别提出了使用放大器偏移电压和电流匹配的 BGR，以及使用偏移电压比较和环路稳定功能的 POR。该电路具有低静态电流，不仅可以生成独立于电压和温度变化的稳定参考电压，而且还提供具有迟滞窗口的高稳健性电源斜坡率耐受上电/掉电复位信号18–24 mV。实验结果表明，具有 2.63%–4.28%/V 的线路调整率 (LNR) 和跨多个芯片的温度系数 (TC) 为 22–32 ppm/°C 的电路的功耗约为 $2.25~\mu \text{W}$ 来自 1V 电源电压。该电路实现了 18.5 nV/的低噪声密度 $\surd $ Hz 在 100 Hz 偏移频率和良好的品质因数 (FoM) 性能。该电路的有效核心面积为 0.014 mm ²，在 0.4–100 ms 的电源斜坡时间下具有固定的复位跳闸电压。