In the nano-scale era, chip temperature has gained a lot of importance due to various reasons. Localized high temperatures in certain regions, commonly known as hotspots, directly affect the performance and reliability of the chip. The proposed work concentrates on temperature-driven floorplanning of chips because incorporating cooling techniques may lead to increase in cost. The proposed approach attempts to evenly distribute power dense components across the chip area in order to suppress hotspots and at the same time generate a layout with aspect ratio nearly 1, as is required in the present day floorplanning scenario. The positions of the blocks in the layout are generated using Boolean Satisfiability (SAT). Apart from peak temperature, wirelength being an important cost factor is also taken into consideration. The proposed technique is successful in decreasing the wirelength and peak temperature for large GSRC, MCNC and IBM HB+ benchmarks.

中文翻译：

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固定轮廓布局的热驱动布局规划

在纳米级时代，由于各种原因，芯片温度变得越来越重要。某些区域的局部高温，俗称热点，直接影响芯片的性能和可靠性。提议的工作集中在温度驱动的芯片布局规划上，因为结合冷却技术可能会导致成本增加。所提出的方法试图在芯片区域内均匀分布功率密集元件，以抑制热点，同时生成纵横比接近 1 的布局，这在当今的平面布局方案中是必需的。布局中块的位置是使用布尔可满足性 (SAT) 生成的。除了峰值温度之外，线长是一个重要的成本因素，也被考虑在内。+基准。