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4H-SiC trench MOSFET with an integrated Schottky barrier diode and L-shaped P+ shielding region
Journal of Semiconductors Pub Date : 2020-09-28 , DOI: 10.1088/1674-4926/41/10/102801
Xiaorong Luo 1 , Ke Zhang 1 , Xu Song 1 , Jian Fang 1 , Fei Yang 2 , Bo Zhang 1
Affiliation  

A novel 4H-SiC trench MOSFET is presented and investigated by simulation in this paper. The device features an integrated Schottky barrier diode and an L-shaped P+ shielding region beneath the gate trench and aside one wall of the gate trench (S-TMOS). The integrated Schottky barrier diode works as a free-wheeling diode in reverse recovery and reverse conduction, which significantly reduces reverse recovery charge (Qrr) and reverse turn-on voltage (VF). The L-shaped P+ region effectively shields the coupling of gate and drain, resulting in a lower gate–drain capacitance (Cgd) and date–drain charge (Qgd). Compared with that of conventional SiC trench MOSFET (C-TMOS), the VF and Qrr of S-TMOS has reduced by 44% and 75%, respectively, with almost the same forward output current and reverse breakdown voltage. Moreover, the S-TMOS reduces Qgd and Cgd by 32% and 22%, respectively, in comparison with C-TMOS.

中文翻译:

具有集成肖特基势垒二极管和 L 形 P+ 屏蔽区的 4H-SiC 沟槽 MOSFET

本文提出并通过仿真研究了一种新型 4H-SiC 沟槽 MOSFET。该器件具有一个集成肖特基势垒二极管和一个 L 形 P+ 屏蔽区,位于栅极沟槽下方和栅极沟槽 (S-TMOS) 的一侧。集成的肖特基势垒二极管在反向恢复和反向导通中用作续流二极管,可显着降低反向恢复电荷 (Qrr) 和反向导通电压 (VF)。L 形 P+ 区有效地屏蔽了栅极和漏极的耦合,从而降低了栅极-漏极电容 (Cgd) 和日期-漏极电荷 (Qgd)。S-TMOS 的 VF 和 Qrr 与传统的 SiC 沟槽 MOSFET (C-TMOS) 相比分别降低了 44% 和 75%,而正向输出电流和反向击穿电压几乎相同。而且,
更新日期:2020-09-28
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