In this work, we present a novel ultra-thin 4H–SiC junctionless tied double gate field effect (DG-JLFET) transistors with a symmetrical dual p⁺ layer (S-D-P DG-JLFET) and the proposed structure compared with a conventional junctionless tied double gate field effect structure (DG-JLFET). By changing the depletion region in the proposed structure and due to the symmetrical dual p⁺ layer, off-current and drain induced barrier lowering (DIBL) effect is improved but on-current reduces a bit. In our paper, we discuss the work function effect on the off and on-current. Also, the effects of temperature on the electron mobility, the threshold voltage, and changing the lengths of the added p⁺ layers have been investigated. Due to the design complexity of the devices in sub 20-nm, the proper models are considered. The ratio of the I_on/I_off current of the proposed structure improves significantly versus the conventional double gate junctionless FET.

在这项工作中，我们提出了一种具有对称双p ⁺层的新型超薄4H–SiC无结双栅场效应（DG-JLFET）晶体管（SDP DG-JLFET），并提出了与常规无结双结双晶体管相比的结构栅极场效应结构（DG-JLFET）。通过更改建议结构中的耗尽区并由于对称的双p ⁺层，可以改善截止电流和漏极引起的势垒降低（DIBL）效果，但导通电流会有所降低。在本文中，我们讨论了功函数对截止电流和导通电流的影响。同样，温度对电子迁移率，阈值电压和改变相加的p ⁺长度的影响层已被调查。由于20纳米以下器件的设计复杂性，因此需要考虑适当的模型。与传统的双栅极无结FET相比，所提出结构的I _on / I _off电流比率得到了显着改善。