Purpose

Very large-scale integration (VLSI) digital signal processing became very popular and is predominantly used in several emerging applications. The optimal design of multirate filter with improvement in performance parameters such as less area, high speed and less power is the challenging task in most of the signal processing applications. This study aims to propose several effective multirate filter structures to accomplish sampling rate conversion.

Design/methodology/approach

The multirate filter structures considered in this work are polyphase filter and coefficient symmetry-based finite impulse response filter. The symmetry scheme particularly brings down the complexity to significant extent. To bring improvement in speed, delay registers are inserted at appropriate path with the help of pipelining and retiming scheme.

Findings

In this paper, the three tasks have been considered. First, the polyphase coefficient symmetry and modified polyphase (MP) structure is designed. Second, the pipelining is applied to the polyphase structure and the obtained results are compared with the polyphase structure. In third, retiming is applied to the polyphase structure and the performance comparison is carried out. The structures are realized for various orders, and the comparative analysis is carried out with the filter order N = 12, 30, 42, 8, 11 and 24 and the results are stated. The performance of all the accomplished structures is analyzed using Altera Quartus with the family cyclone II, device EP2C70F672C6. The results show that the multirate filter using pipelining and retiming offers better performance when examining with the conventional structures. Retimed and pipelined MP structure achieves a speed enhancement of about 33.81% when examining with the conventional polyphase (CP) structure with retiming and pipelining for N = 24 and M = 5. Likewise, the 2/3 structure of pipelined coefficient symmetry approach offers area reduction of about 54.76% over 2/3 structure of pipelined polyphase approach for N = 30 with little reduction in power. The fine grain pipelined and retimed MP structure with N = 11 and M = 3 avails critical path delay reduction of about 28.15% when examining with the corresponding fine grain pipelined and retimed CP structure.

Originality/value

The proposed distinct structures offer better alternative to conventional structures because of the symmetric coefficients, performance enhancement using pipelining and retiming based rate conversion structures. The suggested structures can be used for achieving different rates in software radios.

中文翻译：

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包含重定时和流水线方案的多速率 FIR 滤波器的决定性结构

目的

超大规模集成 (VLSI) 数字信号处理变得非常流行，主要用于几种新兴应用。在大多数信号处理应用中，优化设计多速率滤波器并改进性能参数，例如更小面积、更高速度和更低功耗，是一项具有挑战性的任务。本研究旨在提出几种有效的多速率滤波器结构来完成采样率转换。

设计/方法/方法

在这项工作中考虑的多速率滤波器结构是多相滤波器和基于系数对称的有限脉冲响应滤波器。对称方案尤其在很大程度上降低了复杂性。为了提高速度，在流水线和重定时方案的帮助下，在适当的路径插入延迟寄存器。

发现

在本文中，已经考虑了这三个任务。首先，设计了多相系数对称性和改进的多相（MP）结构。其次，将流水线应用于多相结构，并将获得的结果与多相结构进行比较。第三，将重定时应用于多相结构并进行性能比较。实现了各种阶次的结构，并对滤波器阶数N=12、30、42、8、11和24进行了对比分析，并给出了结果。使用 Altera Quartus 和系列 Cyclone II，器件 EP2C70F672C6 分析所有已完成结构的性能。结果表明，在使用传统结构进行检查时，使用流水线和重定时的多速率滤波器提供了更好的性能。当使用 N = 24 和 M = 5 的重新定时和流水线的传统多相 (CP) 结构进行检查时，重新定时和流水线 MP 结构的速度提高了约 33.81%。同样，流水线系数对称方法的 2/3 结构提供了面积对于 N = 30，比流水线多相方法的 2/3 结构减少约 54.76%，而功率几乎没有减少。当使用相应的细粒度流水线和重定时 CP 结构进行检查时，N = 11 和 M = 3 的细粒度流水线和重定时 MP 结构可使关键路径延迟减少约 28.15%。对于 N = 30，流水线系数对称方法的 2/3 结构比流水线多相方法的 2/3 结构减少了约 54.76% 的面积，而功耗几乎没有降低。当使用相应的细粒度流水线和重定时 CP 结构进行检查时，N = 11 和 M = 3 的细粒度流水线和重定时 MP 结构可使关键路径延迟减少约 28.15%。对于 N = 30，流水线系数对称方法的 2/3 结构比流水线多相方法的 2/3 结构减少了约 54.76% 的面积，而功耗几乎没有降低。当使用相应的细粒度流水线和重定时 CP 结构进行检查时，N = 11 和 M = 3 的细粒度流水线和重定时 MP 结构可使关键路径延迟减少约 28.15%。

原创性/价值

由于对称系数、使用流水线和基于重定时的速率转换结构增强性能，所提出的不同结构提供了对传统结构的更好替代。建议的结构可用于在软件无线电中实现不同的速率。