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A new design strategy for bandwidth and efficiency enhancement in KA band CMOS power amplifier
Circuit World ( IF 0.8 ) Pub Date : 2020-09-17 , DOI: 10.1108/cw-02-2020-0023
Mohammad Sadegh Mirzajani Darestani , Mohammad Bagher Tavakoli , Parviz Amiri

Purpose

The purpose of this paper is to propose a new design strategy to enhance the bandwidth and efficiency of the power amplifier.

Design/methodology/approach

To realize the introduced design strategy, a power amplifier was designed using TSMC CMOS 0.18um technology for operating in the Ka-band, i.e. the frequency range of 26.5-40 GHz. To design the power amplifier, first, a power divider (PD) with a very wide bandwidth, i.e. 1-40 GHz, was designed to cover the whole Ka-band. The designed Doherty power amplifier consisted of two different amplification paths called main and auxiliary. To amplify the signal in each of the two pathways, a cascade distributed power amplifier was used. The main reason for combining the distributed structure and cascade structure was to increase the gain and linearity of the power amplifier.

Findings

Measurements results for designed power dividers are in good agreement with simulations results. The simulation results for the introduced structure of the power amplifier indicated that the gain of the proposed power amplifier at the frequency of 26-35 GHz was more than 30 dB. The diagram of return loss at the input and output of the power amplifier in the whole Ka-band was less than −8dB. The maximum power-added efficiency (PAE) of the designed power amplifier was 80%. The output P1dB of the introduced structure was 36 dB and the output power of the power amplifier was 36 dBm. Finally, the IP3 value of the power amplifier was about 17 dB.

Originality/value

The strategy presented in this paper is based on the usage of Doherty and distributed structures and a new wideband power divider to benefit from their advantages simultaneously.



中文翻译:

KA波段CMOS功率放大器带宽和效率提升的新设计策略

目的

本文的目的是提出一种新的设计策略,以提高功率放大器的带宽和效率。

设计/方法/方法

为了实现所引入的设计策略,使用TSMC CMOS 0.18um 技术设计了一个功率放大器,用于在Ka 波段工作,即26.5-40 GHz 的频率范围。为了设计功率放大器,首先设计了一个具有非常宽带宽(即 1-40 GHz)的功率分配器 (PD),以覆盖整个 Ka 波段。设计的 Doherty 功率放大器由两个不同的放大路径组成,称为主路径和辅助路径。为了放大两条路径中的每一条中的信号,使用了级联分布式功率放大器。结合分布式结构和级联结构的主要原因是为了增加功率放大器的增益和线性度。

发现

设计的功率分配器的测量结果与仿真结果非常吻合。引入功率放大器结构的仿真结果表明,所提出的功率放大器在 26-35 GHz 频率下的增益大于 30 dB。功放输入输出回波损耗图在整个Ka波段小于-8dB。所设计的功率放大器的最大功率附加效率 (PAE) 为 80%。所引入结构的输出 P1dB 为 36 dB,功率放大器的输出功率为 36 dBm。最后,功率放大器的 IP3 值约为 17 dB。

原创性/价值

本文中提出的策略基于使用 Doherty 和分布式结构以及新的宽带功率分配器,以同时受益于它们的优势。

更新日期:2020-09-17
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