In this article, a Schmitt trigger based 12-Transistors(ST12T) static random-access memory (SRAM) bit-cell has been proposed. The Read Power of proposed cell is reduced by 29.17%/ 24.14% /7.66% /5.87% /7.67% /16.62% when compared to 6T/ 7T/ TA8T/ 9T/ PPN10T/ D2p11T SRAM cells. Proposed ST12T cell also shows 1.52\(\times\) and 1.86\(\times\) lesser variability in read current and read power respectively as compared to conventional 6T SRAM cell. Further, the write access time/read access time of the proposed topology are improved by \(1.71 \times /1.82 \times\) as compared to 6T SRAM cell. The read power delay product of proposed ST12T cell is minimum with variation in supply voltage from 0.5 to 1 V when compared with all considered SRAM cells. ST12T SRAM cell also exhibits 26.82% and 8.87% higher read static noise margin and write static noise margin respectively as compared to conventional 6T SRAM cell. This may be attributed to Schmitt trigger design of inverters in core latch of proposed SRAM cell. The proposed bit-cell is free from half select issue and supports bit interleaving format. Authors have used cadence virtuoso tool with Generic Process Design Kit 45 nm technology file to carry out simulation.

本文提出了一种基于施密特触发器的12晶体管（ST12T）静态随机存取存储器（SRAM）位单元。与6T / 7T / TA8T / 9T / PPN10T / D2p11T SRAM单元相比，建议单元的读取功率降低了29.17％/ 24.14％/ 7.66％/ 5.87％/ 7.67％/ 16.62％。与传统的6T SRAM单元相比，拟议的ST12T单元在读取电流和读取功率上的可变性也分别小1.52 \（\ times \）和1.86 \（\ times \）。此外，提出的拓扑的写访问时间/读访问时间提高了（（1.71 \ times / 1.82 \ times \）与6T SRAM单元相比。与所有考虑的SRAM单元相比，建议的ST12T单元的读取功率延迟乘积最小，电源电压在0.5至1 V之间变化。与传统的6T SRAM单元相比，ST12T SRAM单元还分别具有26.82％和8.87％的读取静态噪声容限和写入静态噪声容限。这可以归因于所提出的SRAM单元的核心锁存器中的逆变器的施密特触发器设计。所提出的比特单元没有半选择问题，并且支持比特交织格式。作者已经将cadence virtuoso工具与Generic Process Design Kit 45 nm技术文件一起使用来进行仿真。