The recently proposed stacked nanosheet-field-effect transistor (SNSH-FET) is considered as a promising candidate for continued scaling with silicon. While using punchthrough-stopper-doped (or) ground-plane-doped silicon substrate (PTS-Si substrate) in which the top part of the substrate is doped heavily with the p-type (for nMOS) impurity to avoid punchthrough leakage between the source and the drain. The heavily doped p–n junction formed at the drain–substrate junction acts as a reverse-biased tunnel diode during ${V}_{{\text {DS}}}$ biasing, which leads to large substrate leakage current. We presented SuperSteep-Retrograde silicon substrate (SSR-Si substrate) configuration which reduces the tunneling current by increasing the tunnel barrier width and diminishing the peak electric field at the drain–substrate junction. The SSR-Si substrate is achieved by growing a lightly doped or undoped layer of silicon (SSR-buffer layer) on the PTS-doped substrate. The impact of SSR-buffer layer thickness is studied and the optimal thickness (12 nm) is presented. The vertically stacked channels’ configuration leads to position-dependent current densities in different channels due to position-dependent series resistance. Herein, we present nanosheet width optimization as a solution to achieve homogeneous current ratio between all the channels thereby resulting in better linearity performance. The self-heating and RF performance of the presented SSR-Si substrate is compared with the silicon-on-insulator (SOI) substrate. The results show that SSR-Si substrate can be a better substrate for SNSH-FET because of better self-heating performance.

中文翻译：

---

用于提高堆叠纳米片场效应晶体管性能的优化基板

最近提出的堆叠纳米片场效应晶体管（SNSH-FET）被认为是继续使用硅进行缩放的有希望的候选者。而使用穿通阻止掺杂（或）地平面掺杂的硅衬底（PTS-Si 衬底），其中衬底的顶部重掺杂了 p 型（对于 nMOS）杂质，以避免之间的穿通泄漏源极和漏极。在 ${V}_{{\text {DS}}}$ 偏置期间，在漏极 - 衬底结处形成的重掺杂 p-n 结充当反向偏置隧道二极管，从而导致大衬底漏电流。我们提出了 SuperSteep-Retrograde 硅衬底（SSR-Si 衬底）配置，它通过增加隧道势垒宽度和减少漏极 - 衬底结处的峰值电场来降低隧道电流。SSR-Si 衬底是通过在 PTS 掺杂的衬底上生长轻掺杂或未掺杂的硅层（SSR 缓冲层）来实现的。研究了 SSR 缓冲层厚度的影响，并提出了最佳厚度 (12 nm)。由于位置相关的串联电阻，垂直堆叠的通道配置导致不同通道中的位置相关电流密度。在此，我们将纳米片宽度优化作为实现所有通道之间均匀电流比的解决方案，从而获得更好的线性性能。将所提出的 SSR-Si 衬底的自热和射频性能与绝缘体上硅 (SOI) 衬底进行比较。结果表明，由于具有更好的自热性能，SSR-Si 衬底可以成为更好的 SNSH-FET 衬底。