The threshold voltage variability of the select transistors is an important issue in the development of 3-D NAND flash memory. Particularly, pillar-to-pillar variations in threshold voltage ( ${V}_{\text {T}}$ ) of the ground select transistor (GST) are critical across the wafer. The ${V}_{\text {T}}$ variation is attributed to the nonuniformity in the plug height of the epitaxially grown silicon layers in different pillars. In this article, we propose different techniques to achieve performance uniformity in different strings across the wafer in terms of ${V}_{\text {T}}$ distribution of GST. We show that by optimizing the channel doping and gate metal work function (WF) of the GST, the NAND string ${V}_{\text {T}}$ nonuniformity can be eliminated. It is also shown that ${V}_{\text {T}}$ variability can be further minimized by optimizing GST gate length. Further, we present a two-MOSFET model for the pillar-to-pillar ${V}_{\text {T}}$ variation across the wafer. This study provides important results for designing 3-D NAND memories with higher performance uniformity for the pillar-to-pillar variations in strings across the wafer.

中文翻译：

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减轻 3-D 与闪存中接地选择晶体管的柱间差异

选择晶体管的阈值电压可变性是 3-D NAND 闪存开发中的一个重要问题。特别是，阈值电压的柱间变化（ ${V}_{\text {T}}$ ) 的接地选择晶体管 (GST) 在整个晶圆上至关重要。这 ${V}_{\text {T}}$ 变化归因于不同柱中外延生长的硅层的插塞高度的不均匀性。在本文中，我们提出了不同的技术来实现晶圆上不同串的性能一致性 ${V}_{\text {T}}$ 消费税的分配。我们表明，通过优化 GST 的沟道掺杂和栅极金属功函数 (WF)，NAND 串 ${V}_{\text {T}}$ 可以消除不均匀性。这也表明 ${V}_{\text {T}}$ 通过优化 GST 门长度可以进一步最小化可变性。此外，我们提出了一个用于柱到柱的双 MOSFET 模型 ${V}_{\text {T}}$ 整个晶片的变化。这项研究为设计具有更高性能一致性的 3-D NAND 存储器提供了重要的结果，以应对整个晶圆上串的柱到柱变化。