In this article, we propose an energy-efficient monolithic 3-D (M3D) three-tier SRAM cell with back-end-of-the-line (BEOL) back-gated (BG) MoS2 FETs. The impacts of wire routing resistance and capacitance, gate topology of MoS2 FETs, and the layout optimization of multitier 6T SRAM cells have been comprehensively analyzed for SoC scaling through system-technology co-optimization. SRAM plays an integral role in the performance of SoCs, and the performance can be improved by SRAM on logic integration. Compared with one-tier BG SRAM cell design, the proposed monolithic three-tier BG SRAM cell releases the impact of metal line resistance and shows a 44.3% reduction in cell area, 28.4% improvement in read access time, 21.3% improvement in dynamic energy, and 43.6% improvement in energy-delay product. The energy- and area-efficient three-tier BG SRAM cell enables intelligent functionalities for the area- and energy-constrained edge computing devices.

中文翻译：

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具有用于 SoC 缩放的 BEOL MoS2 FET 的节能单片 3-D SRAM 单元

在本文中，我们提出了一种具有后端 (BEOL) 背栅 (BG) MoS2 FET 的节能单片 3-D (M3D) 三层 SRAM 单元。通过系统技术协同优化，对布线电阻和电容、MoS2 FET 的栅极拓扑结构以及多层 6T SRAM 单元的布局优化的影响进行了全面分析，以实现 SoC 缩放。SRAM对SoC的性能起着不可或缺的作用，SRAM在逻辑集成上可以提高性能。与一层 BG SRAM 单元设计相比，所提出的单片三层 BG SRAM 单元释放了金属线电阻的影响，单元面积减少了 44.3%，读取访问时间提高了 28.4%，动态能量提高了 21.3% , 能量延迟积提高 43.6%。