Multipatterning technology used in 7-nm technology and beyond imposes more and more complex design rules on the layout of cells. The often nonlocal nature of these new design rules is a great challenge not only for human designers but also for existing algorithms. We present a new flow for automatic cell layout generation that is able to deal with these challenges by globally optimizing several design objectives simultaneously. Our transistor placement algorithm not only minimizes the total cell area but at the same time guarantees the routability of the cell and finds a best arrangement and folding of the transistors. Our routing engine computes a detailed routing of all nets simultaneously. It computes a netlength optimal routing using a mixed-integer programming formulation. Additional DFM constraints are added to this model to improve yield and reduce chip manufacturing costs. We present experimental results on current 7-nm designs. Our approach allows to compute optimized layouts within a few minutes, even for large complex cells. The algorithms are used for the design of logic cells compatible with a published 7-nm technology from a leading chip manufacturer where they meet manufacturability requirements and significantly reduced design turn around times.

中文翻译：

---

BonnCell：7nm 时代的自动单元布局

用于 7 纳米技术及以后的多图案技术对单元布局施加了越来越复杂的设计规则。这些新设计规则通常具有非局部性，这不仅对人类设计师而且对现有算法都是一个巨大的挑战。我们提出了一种自动单元布局生成的新流程，它能够通过同时全局优化多个设计目标来应对这些挑战。我们的晶体管布局算法不仅使总单元面积最小化，而且同时保证了单元的可布线性并找到了晶体管的最佳排列和折叠。我们的路由引擎同时计算所有网络的详细路由。它使用混合整数规划公式计算网络长度最佳路由。此模型中添加了额外的 DFM 约束，以提高产量并降低芯片制造成本。我们展示了当前 7 纳米设计的实验结果。我们的方法允许在几分钟内计算优化布局，即使对于大型复杂单元也是如此。这些算法用于设计与领先芯片制造商已发布的 7 纳米技术兼容的逻辑单元，满足可制造性要求并显着缩短设计周转时间。