This work introduces reconfiguration for energy-performance adaptation beyond conventional voltage scaling in microcontroller-based systems. Coordinated thread-level processor and row-level memory reconfiguration are enabled by an architecture-agnostic methodology. The latter requires low design and integration effort while reusing existing macros, including third-party intellectual properties (IPs) in an obfuscated or encrypted form. The methodology represents a drop-in solution that is applicable to extend the energy-performance tradeoff in existing designs. The proposed approach was demonstrated with a testchip implementing an ARM Cortex-M0 processor with 16-KB SRAM in 40 nm. The system demonstrates 1.8X throughput boost at nominal voltage (1.1 V) and 1.3X energy reduction at the minimum energy point (0.51 V) compared to voltage scaling with no reconfiguration. Such energy-performance range extension is achieved at 10.3% area overhead, which is mostly due to processor reconfiguration. Overall, the proposed approach reduces energy in the common case and increases performance when demanded, surpassing the capabilities of conventional voltage scaling, while reusing existing IPs and retaining the original software stack.

中文翻译：

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通过直接方法扩展处理器能量的性能范围，超越电压缩放


这项工作介绍了基于微控制器的系统中超越传统电压缩放的能量性能适应重新配置。协调的线程级处理器和行级内存重新配置是通过与体系结构无关的方法实现的。后者需要很少的设计和集成工作，同时重用现有的宏，包括模糊或加密形式的第三方知识产权 (IP)。该方法代表了一种直接解决方案，适用于扩展现有设计中的能源性能权衡。所提出的方法通过采用 40 nm 工艺、具有 16 KB SRAM 的 ARM Cortex-M0 处理器的测试芯片进行了演示。与无需重新配置的电压缩放相比，该系统在标称电压 (1.1 V) 下的吞吐量提高了 1.8 倍，在最小能量点 (0.51 V) 时能耗降低了 1.3 倍。这种能源性能范围的扩展是在 10.3% 的面积开销下实现的，这主要是由于处理器的重新配置。总体而言，所提出的方法可以减少常见情况下的能耗，并在需要时提高性能，超越传统电压缩放的能力，同时重用现有 IP 并保留原始软件堆栈。