A 4-GHz sub-harmonically injection-locked phase-locked loop (ILPLL) with on-chip calibration is presented. The injection timing and pulsewidth of the injected pulse are self-calibrated to achieve low phase noise. The phase noise of the proposed ILPLL was −112.3 dBc/Hz at 1-MHz offset frequency, whereas that of the conventional PLL was −104.8 dBc/Hz. The measured integrated jitter from 10 kHz to 30 MHz was 710 fs, and the corresponding reference spur level was −61.6 dBc with the proposed calibration technique. Fabricated in a 28-nm CMOS process, the proposed ILPLL occupies 0.09 mm2. Operating at 4 GHz, it consumes 11.4 mW from a 1.0-V power supply.

中文翻译：

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具有自校准注入时序和脉冲宽度的 4GHz 次谐波注入锁定锁相环

介绍了具有片上校准功能的 4GHz 次谐波注入锁定锁相环 (ILPLL)。注入脉冲的注入时间和脉宽是自校准的，以实现低相位噪声。所提出的 ILPLL 的相位噪声在 1-MHz 偏移频率下为 -112.3 dBc/Hz，而传统 PLL 的相位噪声为 -104.8 dBc/Hz。在 10 kHz 至 30 MHz 范围内测得的综合抖动为 710 fs，相应的参考杂散电平为 -61.6 dBc，采用建议的校准技术。采用 28 纳米 CMOS 工艺制造，建议的 ILPLL 占用 0.09 mm2。它在 4 GHz 下运行，从 1.0-V 电源消耗 11.4 mW。