This article presents a four-level pulse-amplitude modulation (PAM4) quarter-rate clock and data recovery circuit (CDR). A quarter-rate linear phase detector (QLPD) is proposed to reduce the recovered clock jitter by removing the dithering jitter of the bang-bang PD. A self-biased phase-locked loop (PLL)-based multiphase clock generator (MCG) with a very wide loop bandwidth (around 600 MHz) is proposed to reduce the MCG power consumption and generate a low-jitter multiphase clock for the quarter-rate operation. Fabricated in a 40-nm CMOS process, the prototype achieves a bit efficiency of 0.46 pJ/bit at 32-Gb/s input data rate. The measured jitter tolerance (JTOL) at the bit error rate (BER) of <; 10-12 is higher than 0.35 UIPP with the corner frequency at about 10 MHz. The measured integrated jitter of the 4-GHz recovered clock is 352.6 fs.

中文翻译：

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使用四分之一速率线性相位检测器和基于自偏置 PLL 的多相时钟发生器的 32Gb/s 0.46pJ/位 PAM4 CDR


本文介绍了一种四级脉冲幅度调制 (PAM4) 四分之一速率时钟和数据恢复电路 (CDR)。提出了四分之一速率线性相位检测器 (QLPD)，通过消除 bang-bang PD 的抖动抖动来减少恢复的时钟抖动。提出了一种基于自偏置锁相环（PLL）的多相时钟发生器（MCG），具有非常宽的环路带宽（约600 MHz），以降低MCG功耗并为四分之一生成低抖动多相时钟。率操作。该原型采用 40 nm CMOS 工艺制造，在 32 Gb/s 输入数据速率下实现了 0.46 pJ/位的位效率。误码率 (BER) 为 < 时测得的抖动容限 (JTOL)； 10-12 高于 0.35 UIPP，转角频率约为 10 MHz。测得的 4 GHz 恢复时钟的集成抖动为 352.6 fs。