An organic charge trapping memory was fabricated employing (3-aminopropyl) triethoxysilane (APTES) self-assembled monolayer (SAM) as the charge trapping layer, and pentacene as the active layer. In the initial trial, APTES SAM is directly in contact with the active layer, which shows inferior memory characteristics exhibiting as small memory window, low reading currents ratio in WRER test, and short retention time. By introducing a thin Polystyrene (PS) tunneling layer between APTES SAM and active layer, all aspects of memory characteristics have been ameliorated, including enlarged memory window, much increased reading currents ratio in WRER test, and much longer retention time. Interestingly, the programming efficiency is not affected by the introduction of the PS tunneling layer, showing a short programming time of less than 1 μs. However, with further increase of PS tunneling layer thickness, the reading current ratio in WRER test and the programming efficiency is slightly decreased. In addition, the retention time is also slightly shorter in terms of thicker PS tunneling layer. Nevertheless, the comprehensive improvement of the memory characteristics by introducing PS tunneling layer enables the potential applications of a nonvolatile memory device.

使用（3-氨基丙基）三乙氧基硅烷（APTES）自组装单层（SAM）作为电荷捕获层，并五苯作为活性层来制造有机电荷捕获存储器。在最初的试验中，APTES SAM直接与有源层接触，这显示出较差的存储特性，表现为较小的存储窗口，WRER测试中的低读取电流比以及较短的保留时间。通过在APTES SAM和有源层之间引入一个薄的聚苯乙烯（PS）隧穿层，改善了存储特性的所有方面，包括扩大了存储范围，在WRER测试中大大提高了读取电流比，以及更长的保留时间。有趣的是，编程效率不受PS隧道层的引入的影响，显示出小于1μs的短编程时间。然而，随着PS隧穿层厚度的进一步增加，WRER测试中的读取电流比和编程效率会略有下降。另外，就较厚的PS隧穿层而言，保留时间也略短。然而，通过引入PS隧穿层全面改善存储特性使非易失性存储设备的潜在应用成为可能。