This paper presents a power-optimized column-parallel cyclic ADC for CMOS image sensor readout circuits. By separating the capacitor and bias current source and floating them in the circuit, the multiplying digital-to-analog converter (MDAC)'s capacitive load and bias current can be significantly decreased during least significant bit (LSB) quantization, which allows the ADC to reduce power consumption while maintaining a constant conversion rate. The residual quantization characteristic of MDAC makes the input-referred noise produced in LSB quantization relatively small, so the additional noise generated by capacitance scaling can be compensated by increasing the capacitance load of the most significant bit (MSB). A 14-bit two-stage column-parallel cyclic ADC is designed using 0.13-μm technology. The simulation results show that the effective-number-of-bit (ENOB) is 13.54 bit under 0.96-μs sampling rate, and the power consumption of each column is 631 μW. Compared with the traditional structure, the power consumption of ADC is reduced by 35.1%, while the performance remains unchanged.

本文提出了一种用于CMOS图像传感器读出电路的功耗优化的列并行循环ADC。通过分离电容器和偏置电流源并将它们浮置在电路中，可以在最小有效位（LSB）量化期间显着降低乘法数模转换器（MDAC）的电容性负载和偏置电流，从而允许ADC在保持恒定转换率的同时降低功耗。MDAC的残留量化特性使LSB量化中产生的输入参考噪声相对较小，因此可以通过增加最高有效位（MSB）的电容负载来补偿电容缩放产生的额外噪声。采用0.13μm技术设计了14位两级列并行循环ADC。仿真结果表明，在0.96-μs采样率下，有效位数（ENOB）为13.54位，每列功耗为631μW。与传统结构相比，ADC的功耗降低了35.1％，而性能却保持不变。