Abstract

An approach to an end-to-end simulation of the electrophysical characteristics of lowly doped sub-25-nm SOI (silicon-on-insulator) CMOS transistors with an asymmetric surrounding gate composed of two sequentially connected materials with different work functions is considered. The approach consists of the consecutive calculation of the 3D potential distribution in the working region, calculation of the current–voltage characteristics, and calculation of the static and dynamic characteristics for a basic logic gate (an inverter). In the context of the discussed approach, the effect of the ratio between the lengths of the gate regions with different work functions on all the key characteristics of the devices (transistors and logic gates based on them) are analyzed. It is demonstrated that the logic gates can operate efficiently at a supply voltage of 0.8 V, which is a prerequisite for the creation of low-voltage circuit engineering.

中文翻译：

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具有非对称环绕栅的SOI CMOS纳米晶体管的特性建模

摘要

考虑一种端到端模拟低掺杂亚25纳米SOI（绝缘体上硅）CMOS晶体管的电物理特性的方法，该晶体管具有不对称的包围栅，该栅由两种具有不同功函数的顺序连接的材料组成。该方法包括连续计算工作区域中的3D电位分布，计算电流-电压特性以及计算基本逻辑门（逆变器）的静态和动态特性。在讨论的方法中，分析了功函数不同的栅极区域的长度之比对器件（晶体管和基于它们的逻辑门）的所有关键特性的影响。