The smart image sensor (SIS) which integrated with both sensor and smart processor has been widely applied in vision-based intelligent perception. In these applications, the linearity of the image sensor is crucial for better processing performance. However, the simple source-follower based readout circuit in the conventional SIS introduces significant nonlinearity. This paper aims to design a low-power in-pixel buffer circuit applied in the high-linearity SIS for the smart perception applications.,The linearity of the SIS is improved by eliminating the non-ideal effects of transistors and cancelling dynamic threshold voltage that changes with the process variation, voltage and temperature. A low parasitic capacitance low leakage switch is proposed to further improve the linearity of the buffer. Moreover, an area-efficient SIS architecture with a sharing mechanism is presented to further reduce the number of in-pixel transistors.,A low parasitic capacitance low leakage switch and a gate-source voltage pre-storage method are proposed to further improve the linearity of the buffer. Nonlinear effects introduced by parasitic capacitance switching leakage, etc., have been investigated and solved by proposing low-parasitic and low-leakage switches. The linearity is improved without a power-hungry operational amplifier-based calibration circuit and a noticeable power consumption increment.,The proposed design is implemented using a standard 0.18-µm CMOS process with the active area of 102 µm2. At the power consumption of 5.6 µW, the measured linearity is −63 dB, which is nearly 27 dB better than conventional active pixel sensor (APS) implementation. The proposed low-power buffer circuit increase not only the performance of the SIS but also the lifetime of the smart perception system.

中文翻译：

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用于智能图像传感器的低功耗像素内缓冲电路

集传感器和智能处理器于一体的智能图像传感器（SIS）已广泛应用于基于视觉的智能感知。在这些应用中，图像传感器的线性度对于更好的处理性能至关重要。然而，传统 SIS 中基于源跟随器的简单读出电路引入了显着的非线性。本文旨在为智能感知应用设计一种应用于高线性SIS的低功耗像素内缓冲电路。通过消除晶体管的非理想效应和取消动态阈值电压，提高SIS的线性度。随工艺变化、电压和温度而变化。提出了低寄生电容低泄漏开关以进一步提高缓冲器的线性度。而且，提出了一种具有共享机制的面积高效 SIS 架构，以进一步减少像素内晶体管的数量。提出了一种低寄生电容低泄漏开关和栅源电压预存储方法，以进一步提高像素内晶体管的线性度。缓冲。通过提出低寄生和低泄漏开关，已经研究和解决了由寄生电容开关泄漏等引入的非线性效应。线性度得到改善，无需耗电的基于运算放大器的校准电路和明显的功耗增量。建议的设计是使用标准 0.18-µm CMOS 工艺实现的，有源面积为 102 µm2。在 5.6 µW 的功耗下，测得的线性度为 −63 dB，比传统的有源像素传感器 (APS) 实施方案好近 27 dB。