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Design of CNTFET-based Ternary ALU using 2:1 Multiplexer based approach
IEEE Transactions on Nanotechnology ( IF 2.1 ) Pub Date : 2020-01-01 , DOI: 10.1109/tnano.2020.3018867
Sharvani Gadgil , Chetan Vudadha

In view of the problems arising due to the scaling of the silicon transistor, different post-silicon, post-binary logic technologies are being explored by researchers. Implementation of Ternary Logic Circuits using Carbon Nanotube Field Effect Transistors (CNTFETs) is one such alternative. CNTFETs are an ideal choice for implementing ternary logic circuits since using CNTFETs multiple threshold voltages can be obtained by changing their physical dimensions. This paper presents a new design for a 2-digit Ternary Arithmetic and Logic Unit (TALU) using CNTFETs. The proposed TALU architecture consists of a function select block, a transmission gate block, and functional modules. In this design, the functional modules are implemented using a 2:1 multiplexer based design approach. This eliminates the need for decoders at the input resulting in lesser number of transistors when compared to existing designs. The proposed 2:1 multiplexer based approach results in lower power consumption in proposed Adder-subtractor and Multiplier modules as compared to existing ones. HSPICE based circuit simulations were performed on the proposed and existing TALU designs. Simulation results show an improvement of up to 96% in power and up to 95% in PDP for the Adder-subtractor and Multiplier modules. An improvement of up to 90% in power and up to 93% in PDP is obtained for the proposed TALU design as compared to the designs existing in the literature.

中文翻译:

使用基于 2:1 多路复用器的方法设计基于 CNTFET 的三元 ALU

鉴于硅晶体管的缩放所引起的问题,研究人员正在探索不同的后硅、后二元逻辑技术。使用碳纳米管场效应晶体管 (CNTFET) 实现三元逻辑电路就是这样一种替代方案。CNTFET 是实现三元逻辑电路的理想选择,因为使用 CNTFET 可以通过改变其物理尺寸来获得多个阈值电压。本文介绍了一种使用 CNTFET 的 2 位三元算术和逻辑单元 (TALU) 的新设计。所提出的 TALU 架构由功能选择块、传输门块和功能模块组成。在本设计中,功能模块使用基于 2:1 多路复用器的设计方法实现。与现有设计相比,这消除了对输入端解码器的需求,从而减少了晶体管数量。与现有模块相比,提议的基于 2:1 多路复用器的方法导致提议的加法器-减法器和乘法器模块的功耗更低。对提议的和现有的 TALU 设计进行了基于 HSPICE 的电路仿真。仿真结果表明,加法器-减法器和乘法器模块的功率提高了 96%,PDP 提高了 95%。与文献中现有的设计相比,所提出的 TALU 设计获得了高达 90% 的功率和高达 93% 的 PDP 改进。与现有模块相比,基于多路复用器的 1 种方法可降低提议的加法器-减法器和乘法器模块的功耗。对提议的和现有的 TALU 设计进行了基于 HSPICE 的电路仿真。仿真结果表明,加法器-减法器和乘法器模块的功率提高了 96%,PDP 提高了 95%。与文献中现有的设计相比,所提出的 TALU 设计获得了高达 90% 的功率和高达 93% 的 PDP 改进。与现有模块相比,基于多路复用器的 1 种方法可降低提议的加法器-减法器和乘法器模块的功耗。对提议的和现有的 TALU 设计进行了基于 HSPICE 的电路仿真。仿真结果表明,加法器-减法器和乘法器模块的功率提高了 96%,PDP 提高了 95%。与文献中现有的设计相比,所提出的 TALU 设计获得了高达 90% 的功率和高达 93% 的 PDP 改进。
更新日期:2020-01-01
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